Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using AOE/Standard recipe with resist mask/SiO2 etch with DUV mask: Difference between revisions
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image:DUV_ox_02_5min 16.jpg|Profile of SiO2 lines etched for 5min with SiO2_res in the AOE, vertical sidewalls, 4µm pitch | image:DUV_ox_02_5min 16.jpg|Profile of SiO2 lines etched for 5min with SiO2_res in the AOE, vertical sidewalls, 4µm pitch | ||
image:DUV_ox_02_top_04.jpg|Bird view of 1µm pitch SiO2 lines, some roughness is seem | image:DUV_ox_02_top_04.jpg|Bird view of 1µm pitch SiO2 lines, some roughness is seem. | ||
image:DUV_ox_01_10min29.jpg|Profile of SiO2 lines etched for 5min with SiO2_res in the AOE, all resist is gone and it has been etched a little down in the Si. | image:DUV_ox_01_10min29.jpg|Profile of SiO2 lines etched for 5min with SiO2_res in the AOE, all resist is gone and it has been etched a little down in the Si. | ||
image:DUV_ox_01_10min32.jpg|Profile of SiO2 lines etched for 5min with SiO2_res in the AOE, all resist is gone and it has been etched a little down in the Si. | image:DUV_ox_01_10min32.jpg|Profile of SiO2 lines etched for 5min with SiO2_res in the AOE, all resist is gone and it has been etched a little down in the Si. |
Latest revision as of 12:57, 3 February 2023
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This page is written by Berit Herstrøm @ DTU Nanolab (BGHE) if nothing else is stated