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= Techniques, hardware and challenges common to all dry etch tools =
= Techniques, hardware and challenges common to all dry etch tools =
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This page contains information that is common to dry etch instruments.  
This page contains information that is common to dry etch instruments.  


 
{| border ="0" align="left" valign="top"
== Hardware and option comparison of the dry etchers at Danchip ==
! style="background:LightGray"| Dry etch page
 
! style="background:#DCDCDC;"|Description
The table below compares the hardware and the options.
 
{| border="2" cellspacing="0" cellpadding="0" align="center"
! colspan="2" style="background:silver; color:black" |
! style="background:silver; color:black" | [[Specific Process Knowledge/Etch/RIE_(Reactive_Ion_Etch)| RIE2]]
! style="background:silver; color:black" | [[Specific Process Knowledge/Etch/ASE_(Advanced_Silicon_Etch)| ASE]]
! style="background:silver; color:black" | [[Specific Process Knowledge/Etch/AOE_(Advanced_Oxide_Etch)| AOE]]
! style="background:silver; color:black" | [[Specific Process Knowledge/Etch/DRIE-Pegasus| DRIE-Pegasus]]
! style="background:silver; color:black" | [[Specific Process Knowledge/Etch/ICP_Metal_Etcher| ICP Metal etch ]]
! style="background:silver; color:black" | [[Specific Process Knowledge/Etch/III-V RIE |III-V RIE ]]
! style="background:silver; color:black" | [[Specific Process Knowledge/Etch/III-V ICP|III-V ICP]]
|- valign="top"
! rowspan="2" style="background:silver; color:black" width="120" |Purpose
! style="background:WhiteSmoke; color:black" | Primary uses
| style="background:WhiteSmoke; color:black"| The RIE chamber for etching of:
* silicon
* silicon oxides/nitrides
The users are allowed to have 5% metal exposed to the plasma
| style="background:WhiteSmoke; color:black"| Formerly the primary silicon etcher; now polymers may also be etched
| style="background:WhiteSmoke; color:black"| Etching of silicon oxides or nitrides
| style="background:WhiteSmoke; color:black"| Silicon etching
| style="background:WhiteSmoke; color:black"| Standard recipes for etching of Al, Cr and Ti, now also etches of W, TiW and Mo
| style="background:WhiteSmoke; color:black"| Etching of silicon oxide, resist, BCB, silicon nitride, InP, InGaAs and GaAs on III-V substrates
| style="background:WhiteSmoke; color:black"| Etching of III-V materials such as GaN, InP/InGaAsP/InGaAs, AlGaAs, GaAs
 
|- valign="top"
! style="background:lightgrey; color:black" | Alternative/backup uses
| style="background:lightgrey; color:black" | Shallow silicon etches
| style="background:lightgrey; color:black" | Backup silicon etcher
| style="background:lightgrey; color:black" |  
| style="background:lightgrey; color:black" | Barc etch
| style="background:lightgrey; color:black" | Silicon etcher
| style="background:lightgrey; color:black" |
| style="background:lightgrey; color:black" |
 
|- valign="top"
! rowspan="7" style="background:silver; color:black" | General description
! style="background:WhiteSmoke; color:black" | Plasma source
| style="background:WhiteSmoke; color:black" | Parallel plate capacitor setup with RF power between the two electrodes
| style="background:WhiteSmoke; color:black" |  Inductively coupled plasma chamber with two RF generators; the coil and platen generator
| style="background:WhiteSmoke; color:black" |  Inductively coupled plasma chamber with two RF generators; the coil and platen generator
| style="background:WhiteSmoke; color:black" | Inductively coupled plasma chamber with two RF generators; the coil (with outer and inner coil) and platen generator
| style="background:WhiteSmoke; color:black" | Inductively coupled plasma chamber with two RF generators; the coil and platen generator
| style="background:WhiteSmoke; color:black" | Parallel plate capacitor setup with RF power between the two electrodes
| style="background:WhiteSmoke; color:black" | Inductively coupled plasma chamber with two RF generators; the coil and platen generator
 
 
|-valign="top"
! style="background:lightgrey; color:black" | Substrate cooling/temperature
| style="background:lightgrey; color:black" | The electrode is oil cooled: Fixed at 20<sup>o</sup>C
| style="background:lightgrey; color:black" | The electrode is oil cooled. Also, Helium backside cooling: -10<sup>o</sup>C to 20<sup>o</sup>C
| style="background:lightgrey; color:black" | The electrode is oil cooled. Also, Helium backside cooling: -10<sup>o</sup>C to 60<sup>o</sup>C
| style="background:lightgrey; color:black" | The electrode is oil cooled. Also, Helium backside cooling: 0<sup>o</sup>C to 50<sup>o</sup>C
| style="background:lightgrey; color:black" | The electrode is oil cooled. Also, Helium backside cooling: -20<sup>o</sup>C to 30<sup>o</sup>C
| style="background:lightgrey; color:black" | The electrode is oil cooled: Fixed at 20<sup>o</sup>C
| style="background:lightgrey; color:black" | The electrode is oil cooled with a special chiller. Also, Helium backside cooling: 20<sup>o</sup>C to 180<sup>o</sup>C
 
|-valign="top"
! style="background:WhiteSmoke; color:black" | Clamping
| style="background:WhiteSmoke; color:black" | No clamping
| style="background:WhiteSmoke; color:black" | Electrostatic clamping (semco electrode)
| style="background:WhiteSmoke; color:black" | Electrostatic clamping (TDESC)
| style="background:WhiteSmoke; color:black" | Electrostatic clamping (TDESC)
| style="background:WhiteSmoke; color:black" | Electrostatic clamping (TDESC)
| style="background:WhiteSmoke; color:black" | No clamping
| style="background:WhiteSmoke; color:black" | Mechanical clamping (weighted clamp with ceramic fingers)
 
|-valign="top"
! style="background:lightgrey; color:black" | Gasses
| style="background:lightgrey; color:black" |
{|
| SF<sub>6</sub>
| O<sub>2</sub>
| CF<sub>4</sub>
|-
|-
| N<sub>2</sub>
| style="background: LightGray"| [[/Comparison| Hardware comparison]]
| Ar
| style="background:#DCDCDC;"| Comparison of the different hardware setups
| CHF<sub>3</sub>
|}
| style="background:lightgrey; color:black" |  
{|
| SF<sub>6</sub>
| O<sub>2</sub>
| C<sub>4</sub>F<sub>8</sub>
|-
|-
| Ar
| style="background: LightGray"| [[/Bonding| Using carrier wafer]]
| CO<sub>2</sub>
| style="background: #DCDCDC"| Processing different sizes of substrates by using a carriers: bonding or not bonding
|}
| style="background:lightgrey; color:black" |  
{|
| SF<sub>6</sub>
| O<sub>2</sub>
| C<sub>4</sub>F<sub>8</sub>
|-
|-
| H<sub>2</sub>
| style="background: LightGray"| [[/OES| Optical Endpoint System]]
| CF<sub>4</sub>
| style="background: #DCDCDC"| Using the OES technique to find endpoints and to diagnose plasmas
| He
|}
|style="background:lightgrey; color:black" |  
{|
| SF<sub>6</sub>
| O<sub>2</sub>
| C<sub>4</sub>F<sub>8</sub>
|-
|-
| Ar
| style="background: LightGray"| [[/LEP| LASER Endpoint System]]
|}
| style="background: #DCDCDC"| Using the LEP technique to find endpoints between interfaces or at a etch depth (in transparent layers)
| style="background:lightgrey; color:black" |  
{|
| SF<sub>6</sub>
| O<sub>2</sub>
| C<sub>4</sub>F<sub>8</sub>
|-
|-
| Ar
| style="background: LightGray"| [[/Data4dryetch| Etch product volatility]]
| CF<sub>4</sub>
| style="background: #DCDCDC"| Links to various tables with data on etch product volatility
| H<sub>2</sub>
|-
| CH<sub>4</sub>
| BCl<sub>3</sub>
| Cl<sub>2</sub>
|-
| HBr
|}
| style="background:lightgrey; color:black" |  
{|
| O<sub>2</sub>
| CHF<sub>3</sub>
| CH<sub>4</sub>
|-
| Ar
| H<sub>2</sub>
|}
| style="background:lightgrey; color:black" |
{|
| SF<sub>6</sub>
| O<sub>2</sub>
| CF<sub>4</sub>
|-
| Ar
| CH<sub>4</sub>
| H<sub>2</sub>
|-
| HBr
| BCl<sub>3</sub>
| Cl<sub>2</sub>
|}
 
|-valign="top"
!  style="background:WhiteSmoke; color:black" | RF generators
| style="background:WhiteSmoke; color:black" | 
* RF generator
|  style="background:WhiteSmoke; color:black" |
* Coil generator
* Platen generator
|  style="background:WhiteSmoke; color:black" |
* Coil generator
* Platen generator
|  style="background:WhiteSmoke; color:black" |
* Coil generator
* Platen generator
* Low frequency platen generator
|  style="background:WhiteSmoke; color:black" |
* Coil generator
* Platen generator
|  style="background:WhiteSmoke; color:black" |
* RF generator
|  style="background:WhiteSmoke; color:black" |
* Coil generator
* Platen generator
 
|-valign="top"
! style="background:lightgrey; color:black" | Substrate loading
| style="background:lightgrey; color:black" | Loading via cluster 2 load lock
| style="background:lightgrey; color:black" | Loading via dedicated two-slot carousel load lock
| style="background:lightgrey; color:black" | Loading via dedicated two-slot carousel load lock
| style="background:lightgrey; color:black" | Loading via dedicated two-slot carousel load lock or via atmospheric cassette loader
| style="background:lightgrey; color:black" | Loading via dedicated two-slot carousel load lock
| style="background:lightgrey; color:black" | Manual loading directly into process chamber
| style="background:lightgrey; color:black" | Loading via dedicated two-slot carousel load lock
 
|-valign="top"
!  style="background:WhiteSmoke; color:black" | Options
| style="background:WhiteSmoke; color:black" | Optical endpoint detector at fixed wavelength
| style="background:WhiteSmoke; color:black" |
* Bosch multiplexing
* Parameter ramping
|  style="background:WhiteSmoke; color:black" |
|  style="background:WhiteSmoke; color:black" |
* Bosch multiplexing
* Parameter ramping
* SOI option
* Optical endpoint detection
|  style="background:WhiteSmoke; color:black" |
* Parameter ramping
* Optical endpoint detection
|  style="background:WhiteSmoke; color:black" |
* Laser endpoint detection
|  style="background:WhiteSmoke; color:black" |  
* Parameter ramping
* Bosch multiplexing
* Optical endpoint detection
* Laser endpoint detection
|-valign="top"
! style="background:silver; color:black"| Allowed materials
| style="background:lightgrey; color:black" |
| style="background:lightgrey; color:black" |
* Silicon
* Fused silica
* Sapphire
* SiC
| style="background:lightgrey; color:black" |
* Silicon
* Fused silica
* Sapphire
* SiC
| style="background:lightgrey; color:black" |
* Silicon
* Fused silica
* Sapphire
* SiC
| style="background:lightgrey; color:black" |
* Silicon
* Fused silica
* Sapphire
* SiC
| style="background:lightgrey; color:black" |
* Silicon
* Fused silica
* Sapphire
* SiC
| style="background:lightgrey; color:black" |
* Silicon
* Fused silica
* Sapphire
* SiC
* GaAs, GaN, InP, with epitaxial layers
| style="background:lightgrey; color:black" |
* Silicon
* Fused silica
* Sapphire
* SiC
* GaAs, GaN, InP, with epitaxial layers
|-
|-
|}
|}
== Temporary bonding of wafers or chips for dry etching ==
=== Purpose ===
Many tools are set up for processing one particular size of wafer. The reasons why a tool processes one size of wafers and not others are numerous - they may include:
* Hardware availability
* Processes required by users
The dry etch tools at Danchip all have a default wafer size and may have other sizes of electrodes available. Other sizes of wafers or chips may also be processed but they will requrie the use of a carrier wafer. Using a carrier is also often required if the side of the wafer facing the electrode has structures.
{| border="2" cellpadding="2" cellspacing="1" style="text-align:center;"
|+ '''Processesing different sizes of wafers or chips in the dry etch tools at Danchip '''
|-
! Tool
! Default substrate size
! Alternative substrate size(s)
! Sizes of wafers or chips that may bonded and processed
|-
![[Specific Process Knowledge/Etch/DRIE-Pegasus|DRIE-Pegasus]]
| 4" wafer
| 6" wafer
| Samples smaller than a 4" wafer
|-
![[Specific Process Knowledge/Etch/RIE (Reactive Ion Etch)|RIE]]
| 4" wafer
| None
| Samples smaller than a 4" wafer
|-
![[Specific Process Knowledge/Etch/ASE (Advanced Silicon Etch)|ASE]]
| 4" wafer
| 6" wafer
| Samples smaller than a 4" wafer
|-
![[Specific Process Knowledge/Etch/AOE (Advanced Oxide Etch)|AOE]]
| 4" wafer
| None
| Samples smaller than a 4" wafer
|-
![[Specific Process Knowledge/Etch/ICP Metal Etcher|ICP Metal Etch]]
| 6" wafer
| 4" wafer
| Samples smaller than a 6" wafer
|-
![[Specific Process Knowledge/Etch/III-V ICP|III-V ICP]]
| 4" wafer
| None
| Samples smaller than a 4" wafer
|-
|}
=== Issues to consider ===
There are several issues to consider when processing a substrate that is lying (either fixed with a bonding material or lying freely) on a carrier.
; Process temperature
: The cooling of a wafer that is lying directly on the electrode is significantly more efficient than if the wafer is lying on top of a carrier. With no bonding material the wafer is essentially only touching the carrier in three points - thus drastically reducing the heat transfer to the electrode. The possible change in substrate temperature may cause the process to drift or the mask to burn away much faster. Using a bonding material such as crystal bond will increase the heat transfer between carrier and substrate.
; Process aggressiveness and material removal
: The chemical etching of materials (for instance if silicon is etched by flourine) releases energy that has to dissipated to the electrode. This release of energy depends on two factors: <ol> <li> The faster the etch rate is, the more material is removed pr second, hence the more heat needs to be dissipated. This means that high power etches are much more sensible to poor heat transfer than low power processes. </li> <li> The larger area of the wafer that is etched, the more material is removed pr second. Hence, wafers with a high density of areas open for etching, will be more sensible to poor heat conductivity than wafers with little opening. </li> </ol>
; Plasma uniformity
: The plasma will adapt to the substrate+carrier sandwich and bow along the edges of the substrate potentially disturbing the electric field that directs the ions towards the surface. This non-uniformity can be important if the substrate is very small.
=== Procedures ===
==== Bonding ====
<ol>
<li>Find a carrier wafer that has the right size. Keep in mind that it matters a great deal if the surface will be etched or not, i.e. if it has oxide or not. </li>
<li>Take a piece of crystalbond from the shelf in cleanroom 1. </li>
<li>Take your items (substrate, carrier wafer, crystalbond and tweezers) to the hotplate in cleanroom 1. </li>
[[image:bonding-n01x.jpg]]
<li>Put the carrier wafer on the hotplate. A 6" wafer will fit not in the recess but it will get sufficiently hot if you leave it there for some seconds longer. </li>
<li>Apply a very thin layer of crystalbond in a circular motion so that it covers some 70 % of the area to be covered by your substrate. Do not apply too much! Little does it.. </li>
<li>Gently put your wafer on the crystalbond. </li>
<li>Using two pairs of tweezers gently massage your substrate in a circular motion in order to distribute the crystalbond evenly between the substrate and carrier while making sure that it doesn’t get exposed on the carrier. </li>
<li>If you are bonding two wafers of the same size (for instance in etch-through applications) make sure that the flats and wafer peripheries are perfectly aligned. </li>
<li>Once the substrate is in the right place, cool the bonded sandwich, for instance by placing it on an aluminium block from the spinner. </li>
<li>Make sure that there’s no trace of crystalbond on the backside of the carrier wafer (the side of the wafer that will face the TDESC) and you’re ready.</li>
</ol>
Keep in mind always to use the same kind of carrier wafer. The process conditions change dramatically if you use a blank silicon wafer instead of a wafer with a few hundred nanometers of thermal oxide when processing a, say, 2" wafer - the area of silicon exposed to plasma is quite different.
==== Debonding ====
Separating a bonded set of wafers or chips may sometimes be tricky and there is no straight forward procedure for all applications. The crystalbond dissolves in water and it melts around 65°C, so one can try one of the following procedures (that increase in aggressiveness).
* Placing the bonded sandwich on the hotplate will release the substrate. Dry with wet cleanroom cloth.
* Wash with DI water
* Wash with DI water, acetone and IPA (any photo resist on your wafer?)
* Wash with DI water, acetone and IPA and use the plasma asher

Latest revision as of 12:50, 3 February 2023

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Techniques, hardware and challenges common to all dry etch tools

This page contains information that is common to dry etch instruments.

Dry etch page Description
Hardware comparison Comparison of the different hardware setups
Using carrier wafer Processing different sizes of substrates by using a carriers: bonding or not bonding
Optical Endpoint System Using the OES technique to find endpoints and to diagnose plasmas
LASER Endpoint System Using the LEP technique to find endpoints between interfaces or at a etch depth (in transparent layers)
Etch product volatility Links to various tables with data on etch product volatility
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