Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using AOE/Standard recipe with resist mask: Difference between revisions

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{{CC-bghe1}}


=The standard recipe=
=The standard recipe=
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|-style="background:Black; color:White"
|-style="background:Black; color:White"
! Parameter
! Parameter
|Recipe name: '''SiO2_res''' ('''SiO2''' etch with '''res'''ist mask)
|Recipe name: '''SiO2_res''' ('''SiO2''' etch with '''res'''ist mask)   
|Variations over '''SiO2_res''' made in 2010 by ''BGHE''  
|-
|-
|Coil Power [W]
|Coil Power [W]
|1300
|1300
|1000-1600
|-
|-
|Platen Power [W]
|Platen Power [W]
|200
|200
|150-300
|-
|-
|Platen temperature [<sup>o</sup>C]
|Platen temperature [<sup>o</sup>C]
|0
|0
|0
|-
|-
|He flow [sccm]
|He flow [sccm]
|174
|174
|174, 300
|-
|-
|C<sub>4</sub>F<sub>8</sub> flow [sccm]
|C<sub>4</sub>F<sub>8</sub> flow [sccm]
|5
|5
|5
|-
|-
|H<sub>2</sub> flow [sccm]
|H<sub>2</sub> flow [sccm]
|4
|4
|0, 4
|-
|-
|Pressure [mTorr]
|Pressure [mTorr]
|4
|4
|2.3, 4
|-
|-
|}
|}


====Etch rates in different materials using the standard "Silicon oxide etch with resist mask" ====
 
===Etch rates in different materials using the standard "Silicon oxide etch with resist mask" ===


{| border="2" cellspacing="2" cellpadding="3"
{| border="2" cellspacing="2" cellpadding="3"
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|-
|-
|Thermal oxide
|Thermal oxide
|'''~230nm/min (5% etch load)''' -  etch load dependency [[/AOE SiO2 etch load dependency|'''see here''']]
|
*'''~230nm/min (5% etch load)''' -  etch load dependency [[/AOE SiO2 etch load dependency|'''see here''']]
*~200 nm/min (100% etch load) ''fall 2016 by Martin Lind Ommen @nanotech'' [[Specific_Process_Knowledge/Etch/Etching_of_Silicon_Oxide#Dry_etch_with_Hard_mask|'''see here''']]
|-
|-
|TEOS oxide (5% load)
|TEOS oxide (5% load)
|'''233nm/min &plusmn;0.7%''' - "&plusmn;" represents the non-uniformity over a 100mm wafer - etched in Marts 2013 ''by LN/BGE@danchip''
|'''233nm/min &plusmn;0.7%''' - "&plusmn;" represents the non-uniformity over a 100mm wafer - etched in Marts 2013 ''by LN/BGHE@nanolab''
|
|-
|-
|PECVD1 (standard) oxide (5% load)
|PECVD1 (standard) oxide (5% load)
|'''242nm/min &plusmn;0.6%''' - "&plusmn;" represents the non-uniformity over a 100mm wafer - etched in Marts 2013 by ''LN/BGE@danchip''
|'''242nm/min &plusmn;0.6%''' - "&plusmn;" represents the non-uniformity over a 100mm wafer - etched in Marts 2013 by ''LN/BGHE@nanolab''
|
|-
|Silicon (10% load)
|32-36 nm/min - January 2019 bghe@nanolab
|-
|-
|Al2O3 from the ALD
|Al2O3 from the ALD
|50nm can be etched in 10min - [[/Etch of Al2O3|'''See results here''']] etched in November 2014 by ''FRSTO@danchip''
 
|
|
*34.2 nm/min (1:6 to SiO2) ''fall 2016 by Martin Lind Ommen @nanotech''
*50nm can be etched in 10min - [[/Etch of Al2O3|'''See results here''']] etched in November 2014 by ''Frederik Stöhr @danchip''
|-
|-
|Silicon rich nitride from furnace B2
|Silicon rich nitride from furnace B2
|136nm was etched in 1min (whole wafer) - etched in October 2015 by ''bghe@danchip''
|136nm was etched in 1min (whole wafer) - etched in October 2015 by ''bghe@nanolab''
|-
|Cr
|
|
6 nm/min (1:33 to SiO2) ''fall 2016 by Martin Lind Ommen @nanotech'' [[Specific_Process_Knowledge/Etch/Etching_of_Silicon_Oxide#Dry_etch_with_Hard_mask|'''see here''']]
|-
|Al
|
25nm/min (1:8 to SiO2) ''fall 2016 by Martin Lind Ommen @nanotech'' [[Specific_Process_Knowledge/Etch/Etching_of_Silicon_Oxide#Dry_etch_with_Hard_mask|'''see here''']]
|-
|-
|}
|}
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<br clear="all" />
<br clear="all" />


====Using different resist masks: results using the standard recipe for "Silicon oxide etch with resist mask" [[Image:section under construction.jpg|70px]] ====
===Using different resist masks: results using the standard recipe for "Silicon oxide etch with resist mask" ===


{| border="2" cellspacing="2" cellpadding="3"
{| border="2" cellspacing="2" cellpadding="3"
|-style="background:DarkGray; color:White"
|-style="background:DarkGray; color:White"
!.
!.
!Az
!Az5214E
!MIR
!MIR701
!nLof
!nLof
!KRF
!KRF
Line 83: Line 90:
|Selectivity to thermal oxide [:1]
|Selectivity to thermal oxide [:1]
|
|
*'''2-3''' - etch load dependency [[/AOE SiO2 etch load dependency|see here]]
*'''2-3''' - etch load dependency [[/AOE SiO2 etch load dependency|'''see here''']]
*'''1.9''' - ''tested November 2015 by BGHE''
*'''1.9''' - ''tested November 2015 by BGHE''
*'''2''' - ''tested December 2022 by BGHE''
|'''1.8''' - ''tested November 2015 by BGHE''
|'''1.8''' - ''tested November 2015 by BGHE''
|'''2.0''' - ''tested November 2015 by BGHE''
|'''2.0''' - ''tested November 2015 by BGHE''
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|-
|-
|Profile [<sup>o</sup>]
|Profile [<sup>o</sup>]
|'''~90'''
|'''~90''' - ''depends on the resist profile before etch, this was obtained with a negative process''
|.
|.
|.
|.
Line 116: Line 124:
|.
|.
|.
|.
|Using the standard oxide recipe (SiO2_res) for 1 min the CSAR looked burned and could not be removed by CSAR stripper (AR600-71). [[Specific_Process_Knowledge/Etch/Etching_of_Silicon_Oxide/SiO2_etch_using_AOE#Etching_with_CSAR_resist |For a better recipe look here]]
|Using the standard oxide recipe (SiO2_res) for 1 min the CSAR looked burned and could not be removed by CSAR stripper (AR600-71). [[Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using AOE/With CSAR resist mask |For a better recipe look here]] <br>
Tried again (2016-08-19 bghe) with 1min with CSAR resist and this time it did not look burned.
|-
|-
|}
|}
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=Variations over the standard "SiO2 etch with resist mask" recipe=
=Variations over the standard "SiO2 etch with resist mask" recipe=
{| border="1" cellspacing="2" cellpadding="2"
|-style="background:Black; color:White"
! Parameter
|Recipe name: '''SiO2_res''' ('''SiO2''' etch with '''res'''ist mask)
|Variations over '''SiO2_res''' made in 2010 by ''BGHE'' 
|-
|Coil Power [W]
|1300
|1000-1600
|-
|Platen Power [W]
|200
|150-300
|-
|Platen temperature [<sup>o</sup>C]
|0
|0
|-
|He flow [sccm]
|174
|174, 300
|-
|C<sub>4</sub>F<sub>8</sub> flow [sccm]
|5
|5
|-
|H<sub>2</sub> flow [sccm]
|4
|0, 4
|-
|Pressure [mTorr]
|4
|2.3, 4
|-
|}
{| border="2" cellspacing="2" cellpadding="3"
{| border="2" cellspacing="2" cellpadding="3"
|-style="background:DarkGray; color:White"
|-style="background:DarkGray; color:White"

Latest revision as of 17:44, 1 February 2023

Feedback to this page: click here

This page is written by Berit Herstrøm @ DTU Nanolab (BGHE) if nothing else is stated

The standard recipe

The standard recipe for oxide etching with photo resist as masking material is called: SiO2_res. The parameters and results so fare are as follows:

Parameter Recipe name: SiO2_res (SiO2 etch with resist mask)
Coil Power [W] 1300
Platen Power [W] 200
Platen temperature [oC] 0
He flow [sccm] 174
C4F8 flow [sccm] 5
H2 flow [sccm] 4
Pressure [mTorr] 4


Etch rates in different materials using the standard "Silicon oxide etch with resist mask"

Material to be etched Etch rate using SiO2_res
Thermal oxide
  • ~230nm/min (5% etch load) - etch load dependency see here
  • ~200 nm/min (100% etch load) fall 2016 by Martin Lind Ommen @nanotech see here
TEOS oxide (5% load) 233nm/min ±0.7% - "±" represents the non-uniformity over a 100mm wafer - etched in Marts 2013 by LN/BGHE@nanolab
PECVD1 (standard) oxide (5% load) 242nm/min ±0.6% - "±" represents the non-uniformity over a 100mm wafer - etched in Marts 2013 by LN/BGHE@nanolab
Silicon (10% load) 32-36 nm/min - January 2019 bghe@nanolab
Al2O3 from the ALD
  • 34.2 nm/min (1:6 to SiO2) fall 2016 by Martin Lind Ommen @nanotech
  • 50nm can be etched in 10min - See results here etched in November 2014 by Frederik Stöhr @danchip
Silicon rich nitride from furnace B2 136nm was etched in 1min (whole wafer) - etched in October 2015 by bghe@nanolab
Cr

6 nm/min (1:33 to SiO2) fall 2016 by Martin Lind Ommen @nanotech see here

Al

25nm/min (1:8 to SiO2) fall 2016 by Martin Lind Ommen @nanotech see here


Using different resist masks: results using the standard recipe for "Silicon oxide etch with resist mask"

. Az5214E MIR701 nLof KRF CSAR
Selectivity to thermal oxide [:1]
  • 2-3 - etch load dependency see here
  • 1.9 - tested November 2015 by BGHE
  • 2 - tested December 2022 by BGHE
 1.8 - tested November 2015 by BGHE 2.0 - tested November 2015 by BGHE ~2 - tested May 2013 by Christian Østergaard @nanotech. .
Profile [o] ~90 - depends on the resist profile before etch, this was obtained with a negative process . . . .
Roughness of the resist after etch - striation on sidewalls see here see here see here . .
Images See here . . See images here .
Comments A negative resist process was done to make the mask. I have not had so good results with a positive resist process. . . . Using the standard oxide recipe (SiO2_res) for 1 min the CSAR looked burned and could not be removed by CSAR stripper (AR600-71). For a better recipe look here

Tried again (2016-08-19 bghe) with 1min with CSAR resist and this time it did not look burned.


Variations over the standard "SiO2 etch with resist mask" recipe

Parameter Recipe name: SiO2_res (SiO2 etch with resist mask) Variations over SiO2_res made in 2010 by BGHE
Coil Power [W] 1300 1000-1600
Platen Power [W] 200 150-300
Platen temperature [oC] 0 0
He flow [sccm] 174 174, 300
C4F8 flow [sccm] 5 5
H2 flow [sccm] 4 0, 4
Pressure [mTorr] 4 2.3, 4


Typical results Variations over SiO2_res made in 2010 by BGHE See results here
Etch rate of thermal oxide ~160-340nm/min
Selectivity to AZ resist [:1] 2.7-4.3
Profile angle 83-90
Images See here
Comments .


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