Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using AOE/Standard recipe with resist mask: Difference between revisions

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=The standard recipe=
=The standard recipe=
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|-style="background:Black; color:White"
|-style="background:Black; color:White"
! Parameter
! Parameter
|Recipe name: '''SiO2_res''' ('''SiO2''' etch with '''res'''ist mask)
|Recipe name: '''SiO2_res''' ('''SiO2''' etch with '''res'''ist mask)   
|Variations over '''SiO2_res''' made in 2010 by ''BGHE''  
|-
|-
|Coil Power [W]
|Coil Power [W]
|1300
|1300
|1000-1600
|-
|-
|Platen Power [W]
|Platen Power [W]
|200
|200
|150-300
|-
|-
|Platen temperature [<sup>o</sup>C]
|Platen temperature [<sup>o</sup>C]
|0
|0
|0
|-
|-
|He flow [sccm]
|He flow [sccm]
|174
|174
|174, 300
|-
|-
|C<sub>4</sub>F<sub>8</sub> flow [sccm]
|C<sub>4</sub>F<sub>8</sub> flow [sccm]
|5
|5
|5
|-
|-
|H<sub>2</sub> flow [sccm]
|H<sub>2</sub> flow [sccm]
|4
|4
|0, 4
|-
|-
|Pressure [mTorr]
|Pressure [mTorr]
|4
|4
|2.3, 4
|-
|-
|}
|}


====Etch rates in different materials using the standard "Silicon oxide etch with resist mask" ====
 
===Etch rates in different materials using the standard "Silicon oxide etch with resist mask" ===


{| border="2" cellspacing="2" cellpadding="3"
{| border="2" cellspacing="2" cellpadding="3"
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|-
|-
|Thermal oxide
|Thermal oxide
|'''~230nm/min (5% etch load)''' -  etch load dependency [[/AOE SiO2 etch load dependency|see here]]
|
*'''~230nm/min (5% etch load)''' -  etch load dependency [[/AOE SiO2 etch load dependency|'''see here''']]
*~200 nm/min (100% etch load) ''fall 2016 by Martin Lind Ommen @nanotech'' [[Specific_Process_Knowledge/Etch/Etching_of_Silicon_Oxide#Dry_etch_with_Hard_mask|'''see here''']]
|-
|-
|TEOS oxide (5% load)
|TEOS oxide (5% load)
|'''233nm/min &plusmn;0.7%''' - "&plusmn;" represents the non-uniformity over a 100mm wafer - etched in Marts 2013 ''by LN/BGE@danchip''
|'''233nm/min &plusmn;0.7%''' - "&plusmn;" represents the non-uniformity over a 100mm wafer - etched in Marts 2013 ''by LN/BGHE@nanolab''
|
|-
|-
|PECVD1 (standard) oxide (5% load)
|PECVD1 (standard) oxide (5% load)
|'''242nm/min &plusmn;0.6%''' - "&plusmn;" represents the non-uniformity over a 100mm wafer - etched in Marts 2013 by ''LN/BGE@danchip''
|'''242nm/min &plusmn;0.6%''' - "&plusmn;" represents the non-uniformity over a 100mm wafer - etched in Marts 2013 by ''LN/BGHE@nanolab''
|
|-
|Silicon (10% load)
|32-36 nm/min - January 2019 bghe@nanolab
|-
|-
|Al2O3 from the ALD
|Al2O3 from the ALD
|50nm can be etched in 10min - [[/Etch of Al2O3|See results here]] etched in November 2014 by ''FRSTO@danchip''
 
|
|
*34.2 nm/min (1:6 to SiO2) ''fall 2016 by Martin Lind Ommen @nanotech''
*50nm can be etched in 10min - [[/Etch of Al2O3|'''See results here''']] etched in November 2014 by ''Frederik Stöhr @danchip''
|-
|-
|Silicon rich nitride from furnace B2
|Silicon rich nitride from furnace B2
|136nm was etched in 1min (whole wafer) - etched in October 2015 by ''bghe@danchip''
|136nm was etched in 1min (whole wafer) - etched in October 2015 by ''bghe@nanolab''
|-
|Cr
|
6 nm/min (1:33 to SiO2) ''fall 2016 by Martin Lind Ommen @nanotech'' [[Specific_Process_Knowledge/Etch/Etching_of_Silicon_Oxide#Dry_etch_with_Hard_mask|'''see here''']]
|-
|Al
|
|
25nm/min (1:8 to SiO2) ''fall 2016 by Martin Lind Ommen @nanotech'' [[Specific_Process_Knowledge/Etch/Etching_of_Silicon_Oxide#Dry_etch_with_Hard_mask|'''see here''']]
|-
|-
|}
|}
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<br clear="all" />
<br clear="all" />


====Using different resist masks: results using the standard recipe for "Silicon oxide etch with resist mask" [[Image:section under construction.jpg|70px]] ====
===Using different resist masks: results using the standard recipe for "Silicon oxide etch with resist mask" ===


{| border="2" cellspacing="2" cellpadding="3"
{| border="2" cellspacing="2" cellpadding="3"
|-style="background:DarkGray; color:White"
|-style="background:DarkGray; color:White"
!.
!.
!Az
!Az5214E
!MIR
!MIR701
!nLof
!nLof
!KRF
!KRF
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|Selectivity to thermal oxide [:1]
|Selectivity to thermal oxide [:1]
|
|
*'''2-3''' - etch load dependency [[/AOE SiO2 etch load dependency|see here]]
*'''2-3''' - etch load dependency [[/AOE SiO2 etch load dependency|'''see here''']]
*'''1.9''' - ''tested November 2015 by BGHE''
*'''1.9''' - ''tested November 2015 by BGHE''
*'''2''' - ''tested December 2022 by BGHE''
|'''1.8''' - ''tested November 2015 by BGHE''
|'''1.8''' - ''tested November 2015 by BGHE''
|'''2.0''' - ''tested November 2015 by BGHE''
|'''2.0''' - ''tested November 2015 by BGHE''
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|-
|-
|Profile [<sup>o</sup>]
|Profile [<sup>o</sup>]
|'''~90'''
|'''~90''' - ''depends on the resist profile before etch, this was obtained with a negative process''
|.
|.
|.
|.
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|.
|.
|.
|.
|Using the standard oxide recipe (SiO2_res) for 1 min the CSAR looked burned and could not be removed by CSAR stripper (AR600-71). [[Specific_Process_Knowledge/Etch/Etching_of_Silicon_Oxide/SiO2_etch_using_AOE#Etching_with_CSAR_resist |For a better recipe look here]]
|Using the standard oxide recipe (SiO2_res) for 1 min the CSAR looked burned and could not be removed by CSAR stripper (AR600-71). [[Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using AOE/With CSAR resist mask |For a better recipe look here]] <br>
Tried again (2016-08-19 bghe) with 1min with CSAR resist and this time it did not look burned.
|-
|-
|}
|}
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<br clear="all" />


==Variations over the standard "SiO2 etch with resist mask" recipe==
=Variations over the standard "SiO2 etch with resist mask" recipe=
{| border="1" cellspacing="2" cellpadding="2"
|-style="background:Black; color:White"
! Parameter
|Recipe name: '''SiO2_res''' ('''SiO2''' etch with '''res'''ist mask)
|Variations over '''SiO2_res''' made in 2010 by ''BGHE'' 
|-
|Coil Power [W]
|1300
|1000-1600
|-
|Platen Power [W]
|200
|150-300
|-
|Platen temperature [<sup>o</sup>C]
|0
|0
|-
|He flow [sccm]
|174
|174, 300
|-
|C<sub>4</sub>F<sub>8</sub> flow [sccm]
|5
|5
|-
|H<sub>2</sub> flow [sccm]
|4
|0, 4
|-
|Pressure [mTorr]
|4
|2.3, 4
|-
|}
 
 
{| border="2" cellspacing="2" cellpadding="3"
{| border="2" cellspacing="2" cellpadding="3"
|-style="background:DarkGray; color:White"
|-style="background:DarkGray; color:White"
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|}
|}


<br clear="all" />
==Etching of micro structures in Aluminum oxide==
''by Fredrik Stöhr''
Aluminum oxide (Al<sub>2</sub>O<sub>3</sub>, Alumina) can be etched with the standard recipe for silicon oxide etching. The parameters including the chuck temperature are identical to the recipe described above: '''SiO2_res'''. ''The etch is probably very physical and gives redeposition, so please consider using a Cl2 etch on the ICP metal instead (BGHE 2015-04-17)'' <br>
'''General Description'''<br>
:Process date: Summer 2014<br>
:Aluminum Oxide with a thickness of 50 nm has been deposited by atomic layer deposition using the respective standard recipe.<br>
:Substrates: Blank 525 µm Silicon wafers or Silicon wafers with thermally grown Silicon Oxide prior to Alumina deposition. <br>
:Mask: [XOP8] AZ5214E 1.5 µm thick (HMDS pretreatment, 6-inch aligner 3 sec exposure, 60 sec development).
:Etch Load (Total Exposed SiO2): ~ 5 %<br>
:Post process: O2 Plasma Ashing 10 min
{| border="1" cellspacing="1" cellpadding="1" align="middle"
![[image:FRSTO Al2O3 AOE 1 Top 05.jpg|300x300px|thumb|left|
Etch time: 3 min. Substrate: Blank Si. <br>
Bird View. The dark area is Silicon. The bright area is Alumina. The black flakes stem from redeposited sputtered material and is most likely aluminum oxide, since it is almost non-volatile in the used plasma chemistry. It must have been laying on top of the photo resist mask and landed on the alumina after resist ashing.
]]
![[image:FRSTO Al2O3 AOE 2 Top 04.jpg|300x300px|thumb|left|
Etch time: 3 min. Substrate: Blank Si. <br>
Bird View. Close-up. The dark area is Silicon. The bright area is Alumina. The black flakes stem from redeposited sputtered material.
]]
![[image:FRSTO Al2O3 AOE 3 Top Tilt30 08.jpg|300x300px|thumb|left|
Etch time: 3 min. Substrate: Blank Si. <br>
Bird View. Close-up. The dark area is Silicon. The bright area is Alumina.
]]
![[image:FRSTO Al2O3 AOE 4 Cross06.jpg|300x300px|thumb|left|
Etch time: 3 min<br>
Cross section of deep reactive ion etched silicon (DRIE Pegasus), where the structured alumina was used as a mask. Remarkably, the etch selectivity of Alumina to Silicon is >1:10000.
]]
|-
|}
{| border="1" cellspacing="1" cellpadding="1" align="middle"
![[image:FRSTO Al2O3 AOE 5 Top Tilt30 05.jpg|300x300px|thumb|left|
Etch time: 10 min. Substrate: Blank Si. <br>
The view tilt angle is 30°. The edge is corrugated, which is most likely to the corrugated resist mask.
]]
![[image:FRSTO Al2O3 AOE 6 Top Tilt30 04.jpg|300x300px|thumb|left|
Etch time: 10 min. Substrate: Blank Si. <br>
The view tilt angle is 30°. Vertical striations and considerable over-etching of the Silicon substrate are apparent. It seems as if less material has been redeposited, which may be due to the prolonged etch time in comparison to the above.
]]
![[image:FRSTO Al2O3 AOE 7 Top Tilt30 01.jpg|300x300px|thumb|left|
Etch time: 10 min. Substrate: Blank Si. <br>
The view tilt angle is 30°. Vertical striations and considerable over-etching of the Silicon substrate are apparent. It seems as if less material has been redeposited, which may be due to the prolonged etch time in comparison to the above.
]]
|-
|}
{| border="1" cellspacing="1" cellpadding="1" align="middle"
![[image:FRSTO Al2O3 AOE 8 AOE15min Top Tilt45 21.jpg|300x300px|thumb|left|
Etch time: 15 min. Substrate: Silicon with 1 µm thermally grown SiO2 <br>
The view tilt angle is 45°. Alumina and Silicon Oxide may be etched in one go.
]]
![[image:FRSTO Al2O3 AOE 9 AOE15min Top Tilt45 27.jpg|300x300px|thumb|left|
Etch time: 15 min. Substrate: Silicon with 1 µm thermally grown SiO2 <br>
The view tilt angle is 45°. Alumina and Silicon Oxide may be etched in one go. Considerable over-etchign of the Silicon substrate is apparent.
]]
![[image:FRSTO Al2O3 AOE 10 AOE15min Top Tilt45 31.jpg|300x300px|thumb|left|
Etch time: 15 min. Substrate: Silicon with 1 µm thermally grown SiO2 <br>
The view tilt angle is 45°. Alumina and Silicon Oxide may be etched in one go. Considerable over-etchign of the Silicon substrate is apparent.
]]
|-
|}
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<br clear="all" />

Latest revision as of 17:44, 1 February 2023

Feedback to this page: click here

This page is written by Berit Herstrøm @ DTU Nanolab (BGHE) if nothing else is stated

The standard recipe

The standard recipe for oxide etching with photo resist as masking material is called: SiO2_res. The parameters and results so fare are as follows:

Parameter Recipe name: SiO2_res (SiO2 etch with resist mask)
Coil Power [W] 1300
Platen Power [W] 200
Platen temperature [oC] 0
He flow [sccm] 174
C4F8 flow [sccm] 5
H2 flow [sccm] 4
Pressure [mTorr] 4


Etch rates in different materials using the standard "Silicon oxide etch with resist mask"

Material to be etched Etch rate using SiO2_res
Thermal oxide
  • ~230nm/min (5% etch load) - etch load dependency see here
  • ~200 nm/min (100% etch load) fall 2016 by Martin Lind Ommen @nanotech see here
TEOS oxide (5% load) 233nm/min ±0.7% - "±" represents the non-uniformity over a 100mm wafer - etched in Marts 2013 by LN/BGHE@nanolab
PECVD1 (standard) oxide (5% load) 242nm/min ±0.6% - "±" represents the non-uniformity over a 100mm wafer - etched in Marts 2013 by LN/BGHE@nanolab
Silicon (10% load) 32-36 nm/min - January 2019 bghe@nanolab
Al2O3 from the ALD
  • 34.2 nm/min (1:6 to SiO2) fall 2016 by Martin Lind Ommen @nanotech
  • 50nm can be etched in 10min - See results here etched in November 2014 by Frederik Stöhr @danchip
Silicon rich nitride from furnace B2 136nm was etched in 1min (whole wafer) - etched in October 2015 by bghe@nanolab
Cr

6 nm/min (1:33 to SiO2) fall 2016 by Martin Lind Ommen @nanotech see here

Al

25nm/min (1:8 to SiO2) fall 2016 by Martin Lind Ommen @nanotech see here


Using different resist masks: results using the standard recipe for "Silicon oxide etch with resist mask"

. Az5214E MIR701 nLof KRF CSAR
Selectivity to thermal oxide [:1]
  • 2-3 - etch load dependency see here
  • 1.9 - tested November 2015 by BGHE
  • 2 - tested December 2022 by BGHE
 1.8 - tested November 2015 by BGHE 2.0 - tested November 2015 by BGHE ~2 - tested May 2013 by Christian Østergaard @nanotech. .
Profile [o] ~90 - depends on the resist profile before etch, this was obtained with a negative process . . . .
Roughness of the resist after etch - striation on sidewalls see here see here see here . .
Images See here . . See images here .
Comments A negative resist process was done to make the mask. I have not had so good results with a positive resist process. . . . Using the standard oxide recipe (SiO2_res) for 1 min the CSAR looked burned and could not be removed by CSAR stripper (AR600-71). For a better recipe look here

Tried again (2016-08-19 bghe) with 1min with CSAR resist and this time it did not look burned.


Variations over the standard "SiO2 etch with resist mask" recipe

Parameter Recipe name: SiO2_res (SiO2 etch with resist mask) Variations over SiO2_res made in 2010 by BGHE
Coil Power [W] 1300 1000-1600
Platen Power [W] 200 150-300
Platen temperature [oC] 0 0
He flow [sccm] 174 174, 300
C4F8 flow [sccm] 5 5
H2 flow [sccm] 4 0, 4
Pressure [mTorr] 4 2.3, 4


Typical results Variations over SiO2_res made in 2010 by BGHE See results here
Etch rate of thermal oxide ~160-340nm/min
Selectivity to AZ resist [:1] 2.7-4.3
Profile angle 83-90
Images See here
Comments .


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