Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using AOE

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This page is written by Berit Herstrøm @ DTU Nanolab (BGHE) if nothing else is stated

What masking material should I choose when etching SiO2/glass in the AOE?

Photoresist mask - not too deep etches
Etching SiO2 with resist as masking material is the prefered masking material for many purposes. The main reason for using photo resist as masking material is that it is easy and fast to make and easy to remove afterwards. The selectivity of resist to SiO2 is in the range of 2-4.

The main draw back when using photoresist as masking material is heating of the substrate during the etch. SiO2 is a hard material to etch and therefore needs a high DC bias to allow the ion bombardment to be enegetic enough to etch the SiO2. This ion bombardment heats up the surface and even when cooling the platen to zero degrees Celcius the resist mask can exceed 100 degrees Celcius. Combined with the fact that the plasma UV hardens the surface of the resist this can create crumpled resist surface and perforated egdes, see images here. Etching a few microns down in the SiO2 normally does not heat up the resist too much but when etching deeper like 5-10µm there is a large change for getting problems with overheating the resist.

Si/P-Si mask - deeper etches
P-Si is a good masking layer for deeper etches. The selectivity to SiO2 is measured to be better than 1:15. The P-Si on the back side seems to prevent declamping of a APOX (thick oxide) substrate during a deep etch on a high load wafer (e.g. 50% load), contrary to using photoresist mask on the APOX substrate. The wafer bow is created when removing part of the top oxide layer due to stress in the oxide layers.

Drawbacks: the recipe we have now is giving a high line width reduction (1µm when etching 7.5µm down). There is tendency for silicon masks to sputter at an angle near 45 degrees, so even if it seems like there is enough Si mask on top this will given mask recession at the edges and lead to an angled sidewall profile. Take a look at some recipes and results

Al mask - deeper etches - more redeposition

Al is allowed as masking material but we do not advise it. It can however be useful under some circumstances. It is expected to have a high selectivity to SiO2 greater than 50.

Draw back: The drawback is that Al does not form any volatile products with the Flour gasses. This means that any Al sputtered of has the chance of getting redeposited on the surface. AlF3 sputters of very easily.

Cr mask - deeper etches/high aspect ratio etches where the other materials cannot be used

Cr works well as masking material but due to cross contamination issues we prefer to avoid Cr in the machine. Cr does in contrary to Al form some volatile components with the flour gasses and therefore redeposition problems are not so severe. We do allow Cr as masking material when the other masking materials cannot be used.

So fare it has been found useful for etching nanostructures in quartz substrates and has briefly been tested in etching of fused silica. Etching with flour gasses and small amount of O2 Cr seems to etch well, so for high selectivity you must avoid small amounts of O2 in the recipe.

QC on the AOE

Quality Control (QC) for AOE

The QC procedure for AOE - requires login The newest QC data for AOE - requires login QC Recipe: QC mres C4F8 flow 5 sccm H2 flow 4 sccm He flow 174 sccm Pressure 4 mTorr Coil power 1300 W Platen power 200 W Platen Temperature 20 deg. C Etch Load 100% QC limits AOE Etch rate in SiO2 180 - 195 nm/min Non-uniformity <2.28 %

Standard silicon oxide etch using resist as masking material

• The standard recipe for etching SiO2 with resist mask - results and variations

• Slow etch of SiO2 with resist as masking material - e.g. for use with carrier

• Etching with CSAR resist as masking material

Etching of micro structures in Silicon Oxide with PolySi as masking material

The choice of recipe depends on your preferences. Some different etch recipes are given here. These are all variations over the same recipe so the differences are minor. You can choose between getting:

• High etch rate
• Low line width reduction
• Good wafer uniformity
• High selectivity to Si mask

Etching SiO2 with hard mask (metal or dielectrics)

So fare it has been found useful for

• etching nanostructures in quartz substrates

and has briefly been tested in

• etching of fused silica

It has also been tested etching SiO2 layer on silicon wafers:

• SiO2 etching with hard mask

Limitations using the AOE

Wafer bow

There is a limit to how much the wafer can bow and still be clamped on the chuck. The limit can maybe vary a little over time and may also depend on the material on the backside of the substrate. On a 100mm Si wafer with SiO2 on the backside (<10µm) we expect the limit to be around 50µm bow (when the back side surface is convex).

A bow will be created when etching the top oxide layer on a wafer with oxide on both sides. For a larger etch load the bow will be more severe for a specific etch depth when for a smaller etch load. I have been able to etch much deeper in SiO2 with a P-Si mask than with a photo resist mask on a wafer with 50% load. When using photoresist the wafer stopped clamping during the etch after just a few µm. With P-Si I could etch 15µm without problems. I expect this to be due to a combination of P-Si on the back side clamping much better and P-Si on the back side helping to reduce the bow.

Transparent wafers

Transparent wafers are a challange for two reasons. 1. In the load lock the LASER detection system that is used to detect the wafer during mapping cannot detect a completely transparent wafer. 2. A transparent wafer is either quartz or fused silicon. These materials are very difficult to clamp electrostatically and will therefore not be able to pass the He leak up test succesfully.

1. The first issue may be overcome by using a non-transparent masking material or adding a non-transparent material on the back side of the wafer (could be aluminium).
2. The second issue may be overcome by reducing the He back side pressure or reducing the He back side cooling completely. Another way to solve it is to either bond the transparent wafer to a silicon wafer before transfering it into chamber or deposite a more conducting layer on the backside of the wafer. This could be aluminium but also 1-2µm P-Si may be enough.