Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using AOE: Difference between revisions

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[[Specific Process Knowledge/Etch/AOE (Advanced Oxide Etch) |Click here to go to the AOE equipment page]]
{{CC-bghe1}}


=What masking material should I choose when etching SiO2/glass in the AOE?=
=What masking material should I choose when etching SiO2/glass in the AOE?=
'''Photoresist mask - not too deep etches''' <br/>
'''Photoresist mask - not too deep etches''' <br/>
Etching SiO2 with resist as masking material is the prefered masking material for many purposes. The main reason for using photo resist as masking material is that it is easy and fast to make and easy to remove afterwards. The selectivity of resist to SiO2 is in the range of 3-4.  
Etching SiO2 with resist as masking material is the prefered masking material for many purposes. The main reason for using photo resist as masking material is that it is easy and fast to make and easy to remove afterwards. The selectivity of resist to SiO2 is in the range of 2-4.  


''The main draw back when using photoresist as masking material'' is heating of the substrate during the etch. SiO2 is a hard material to etch and therefore needs a high DC bias to allow the ion bombardment to be enegetic enough to etch the SiO2. This ion bombardment heats up the surface and even when cooling the platen to zero degrees Celcius the resist mask can exceed 100 degrees Celcius. Combined with the fact that the plasma UV hardens the surface of the resist this can create crumpled resist surface and perforated egdes, see images [[/Images of m_resist etches|here]]. Etching a few microns down in the SiO2 normally does not heat up the resist too much but when etching deeper like 5-10µm there is a large change for getting problems with overheating the resist.
The main draw back when using photoresist as masking material is heating of the substrate during the etch. SiO2 is a hard material to etch and therefore needs a high DC bias to allow the ion bombardment to be enegetic enough to etch the SiO2. This ion bombardment heats up the surface and even when cooling the platen to zero degrees Celcius the resist mask can exceed 100 degrees Celcius. Combined with the fact that the plasma UV hardens the surface of the resist this can create crumpled resist surface and perforated egdes, see images [[/Images of m_resist etches|here]]. Etching a few microns down in the SiO2 normally does not heat up the resist too much but when etching deeper like 5-10µm there is a large change for getting problems with overheating the resist.




'''Si/P-Si mask - deeper etches''' <br/>
'''Si/P-Si mask - deeper etches''' <br/>
P-Si is a good masking layer for deeper etches. The selectivity to SiO2 is measured to be better than 1:15. The P-Si on the back side seems to prevent declamping of a APOX substrate during a deep etch on a high load wafer (e.g. 50% load), contrary to using photo resist mask on the APOX substrate. The wafer bow is created when removing part of the top oxide layer due to stress in the oxide layers.
P-Si is a good masking layer for deeper etches. The selectivity to SiO2 is measured to be better than 1:15. The P-Si on the back side seems to prevent declamping of a APOX (thick oxide) substrate during a deep etch on a high load wafer (e.g. 50% load), contrary to using photoresist mask on the APOX substrate. The wafer bow is created when removing part of the top oxide layer due to stress in the oxide layers.


Draw backs: the recipe we have now is giving a high line width reduction (1µm when etching 7.5µm down).
Drawbacks: the recipe we have now is giving a high line width reduction (1µm when etching 7.5µm down). There is tendency for silicon masks to sputter at an angle near 45 degrees, so even if it seems like there is enough Si mask on top this will given mask recession at the edges and lead to an angled sidewall profile.
Take a look at some [[Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using AOE#Etching of micro structures in Silicon Oxide with PolySi as masking material|recipes and results]]
Take a look at some [[Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using AOE#Etching of micro structures in Silicon Oxide with PolySi as masking material|recipes and results]]


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'''Al mask - deeper etches - more redeposition''' <br/>
'''Al mask - deeper etches - more redeposition''' <br/>


Al is allowed as masking material but we do not advise it. It can however be useful under some curcumstances. It is expected to have a high selectivity to SiO2 greater than 50.  
Al is allowed as masking material but we do not advise it. It can however be useful under some circumstances. It is expected to have a high selectivity to SiO2 greater than 50.  


Draw back: The draw back is that Al does not form any volatile products with the Flour gasses. This means that any Al sputtered of has the chance of getting redeposited on the surface.
Draw back: The drawback is that Al does not form any volatile products with the Flour gasses. This means that any Al sputtered of has the chance of getting redeposited on the surface. AlF3 sputters of very easily.




Line 27: Line 30:
Cr works well as masking material but due to cross contamination issues we prefer to avoid Cr in the machine. Cr does in contrary to Al form some volatile components with the flour gasses and therefore redeposition problems are not so severe. We do allow Cr as masking material when the other masking materials cannot be used.  
Cr works well as masking material but due to cross contamination issues we prefer to avoid Cr in the machine. Cr does in contrary to Al form some volatile components with the flour gasses and therefore redeposition problems are not so severe. We do allow Cr as masking material when the other masking materials cannot be used.  


So fare it has been found useful for [[Specific Process Knowledge/Etch/AOE (Advanced Oxide Etch)/Quartz etch using AOE|etching nanostructures in quartz substrates]].
So fare it has been found useful for [[Specific Process Knowledge/Etch/AOE (Advanced Oxide Etch)/Quartz etch using AOE|etching nanostructures in quartz substrates]] and has briefly been tested in [[Specific Process Knowledge/Etch/Etching of Bulk Glass/AOE etching of fused silica|etching of fused silica]]. Etching with flour gasses and small amount of O2 Cr seems to etch well, so for high selectivity you must avoid small amounts of O2 in the recipe.


<br clear="all" />
<br clear="all" />


=Etching of micro structures in Silicon Oxide with '''resist as masking material'''=
=QC on the AOE=
{| border="1" cellspacing="2" cellpadding="2" colspan="3"
{| border="1" cellspacing="2" cellpadding="2" colspan="3"
|bgcolor="#98FB98" |'''Quality Controle (QC) for AOE'''
|bgcolor="#98FB98" |'''Quality Control (QC) for AOE'''
|-
|-
|
|
*[http://labmanager.danchip.dtu.dk/d4Show.php?id=2920&mach=115 The QC procedure for AOE]<br>
*[http://labmanager.dtu.dk/d4Show.php?id=2920&mach=115 The QC procedure for AOE - requires login]<br>
*[http://www.labmanager.danchip.dtu.dk/view_binary.php?type=data&mach=115 The newest QC data for AOE]<br>
*[https://labmanager.dtu.dk/view_binary.php?type=data&mach=115 The newest QC data for AOE - requires login]<br>
{| {{table}}
{| {{table}}
| align="center" |  
| align="center" |  
Line 87: Line 90:


<br/>
<br/>
=Standard silicon oxide etch using resist as masking material=


=Standard silicon oxide etch using '''resist as masking material'''=


==[[/Standard recipe with resist mask|The standard recipe for etching SiO2 with resist mask]]==


==[[/Slow etch with resist mask|Slow etch of SiO2 with resist as masking material - e.g. for use with carrier]]==
*[[/Standard recipe with resist mask|The '''standard recipe''' for etching SiO2 with resist mask]] - ''results and variations''


==[[/With CSAR resist mask|Etching with '''CSAR resist''' as masking material]]==
*[[/Slow etch with resist mask|'''Slow etch''' of SiO2 with resist as masking material]] - ''e.g. for use with carrier''
 
*[[/With CSAR resist mask|Etching with '''CSAR resist''' as masking material]]


=Etching of micro structures in Silicon Oxide with '''PolySi as masking material'''=
=Etching of micro structures in Silicon Oxide with '''PolySi as masking material'''=


The choice of recipe depends on your preferences. Some different etch rate recipes are given here. You can choose between getting  
The choice of recipe depends on your preferences. Some different etch recipes are given here. These are all variations over the same recipe so the differences are minor. You can choose between getting:
*[[Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using AOE#High etch rate recipe|High etch rate]]  
*[[/PolySi mask#High etch rate recipe|High etch rate]]  
*[[Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using AOE#Low line width reduction recipe|Low line width reduction]]
*[[/PolySi mask#Low line width reduction recipe|Low line width reduction]]
*[[Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using AOE#Good wafer uniformity recipe|Good wafer uniformity]]  
*[[/PolySi mask#Good wafer uniformity recipe|Good wafer uniformity]]  
*[[Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using AOE#High selectivity to Si-mask recipe| High selectivity to Si mask]]
*[[/PolySi mask#High selectivity to Si-mask recipe| High selectivity to Si mask]]
 
<br/>
==High etch rate recipe==
{| border="2" cellspacing="2" cellpadding="3"
|-style="background:Black; color:White"
!Parameter
|Recipe name: '''SiO2_psi''' ('''SiO2''' etch with '''pSi''' mask)
|-
|Coil Power [W]
|1300
|-
|Platen Power [W]
|500
|-
|Platen temperature [<sup>o</sup>C]
|60
|-
|He flow [sccm]
|300
|-
|C<sub>4</sub>F<sub>8</sub> flow [sccm]
|18
|-
|H<sub>2</sub> flow [sccm]
|0
|-
|Pressure [mTorr]
|4
|-
|}
 
 
{| border="2" cellspacing="2" cellpadding="3"
|-style="background:DarkGray; color:White"
!Typical results
!PolySi mask - ''tested by Yunhong Ding @fotonik''
!PolySi mask - ''tested Feb. 2012 by bge@danchip''
|-
|Etch rate
|~0.55 µm/min
|0.50 µm/min
|-
|Selectivity
|1:~10
|1:17
|-
|SiO2 etch uniformity
|not tested
|&plusmn;4.5% over a 100mm wafer
|-
|Profile [<sup>o</sup>]
|not tested
|see images
|-
|Images
|.
|[[/Images of m_PolySi1 etches|See here]]
|-
|Comments
|.
|Line width reduction is about 2.5µm when etching 12.5µm down. See the images to get more info on this
|-
|}
 
<br/>
 
==Low line width reduction recipe==
It is difficult to get very low line width reduction using P-Si as masiking material. This is due to the fact that the etch gas C4F8 that is used to etch SiO2 also etches Si very well. The best result so fare is given here:
 
{| border="2" cellspacing="2" cellpadding="3"
|-style="background:Black; color:White"
!Parameter
!Poly Si mask
|-
|Coil Power [W]
|1100
|-
|Platen Power [W]
|170
|-
|Platen temperature [<sup>o</sup>C]
|50
|-
|He flow [sccm]
|450
|-
|C<sub>4</sub>F<sub>8</sub> flow [sccm]
|12
|-
|H<sub>2</sub> flow [sccm]
|0
|-
|Pressure [mTorr]
|6
|-
|Spacer settings [mm]
|100
|-
|}
 
 
{| border="2" cellspacing="2" cellpadding="3"
|-style="background:DarkGray; color:White"
!Typical results
!PolySi mask - ''tested spring. 2012 by bge@danchip''
|-
|Etch rate
|~0.25 µm/min
|-
|Selectivity
|1:12
|-
|SiO2 etch uniformity
|&plusmn;1.1% over a 100mm wafer
|-
|Profile [<sup>o</sup>]
|see images
|-
|Images
|[[/Images of AOEpsiB_8|See here]]
|-
|Comments
|Line width reduction is about 1µm when etching 7.5µm down. See the images to get more info on this
|-
|}
 
<br/>
 
==Good wafer uniformity recipe ==
This recipe has not been optimized to get as uniformity as possible but was just the one with the lowest non-uniformity among the recipes I have tested.
 
{| border="2" cellspacing="2" cellpadding="3"
|-style="background:Black; color:White"
!Parameter
!Poly Si mask
|-
|Coil Power [W]
|1300
|-
|Platen Power [W]
|350
|-
|Platen temperature [<sup>o</sup>C]
|60
|-
|He flow [sccm]
|450
|-
|C<sub>4</sub>F<sub>8</sub> flow [sccm]
|18
|-
|H<sub>2</sub> flow [sccm]
|7
|-
|Pressure [mTorr]
|8
|-
|Spacer settings [mm]
|0
|-
|}
 
 
{| border="2" cellspacing="2" cellpadding="3"
|-style="background:DarkGray; color:White"
!Typical results
!PolySi mask - ''tested spring. 2012 by bge@danchip''
|-
|Etch rate
|~0.40 µm/min
|-
|Selectivity
|1:10
|-
|SiO2 etch uniformity (&plusmn;(max-min/2*avg)
|&plusmn;0.54% over a 100mm wafer
|-
|Profile [<sup>o</sup>]
|see images
|-
|Images
|[[/Images of AOEpsi10|See here]]
|-
|Comments
|Line width reduction is about 3µm when etching 14µm down. See the images to get more info on this
|-
|}


<br/>
<br/>


==High selectivity to Si-mask recipe==
=Etching SiO2 with '''hard mask (metal or dielectrics)'''=
This recipe has not been optimize to get as good selectivity as possible but was just the one with the highest selectivity among the recipes I have tested.
So fare it has been found useful for
 
*[[Specific Process Knowledge/Etch/AOE (Advanced Oxide Etch)/Quartz etch using AOE|etching nanostructures in quartz substrates]]  
and has briefly been tested in
{| border="2" cellspacing="2" cellpadding="3"
*[[Specific Process Knowledge/Etch/Etching of Bulk Glass/AOE etching of fused silica|etching of fused silica]]
|-style="background:Black; color:White"
!Parameter
!Poly Si mask
|-
|Coil Power [W]
|1300
|-
|Platen Power [W]
|350
|-
|Platen temperature [<sup>o</sup>C]
|20
|-
|He flow [sccm]
|450
|-
|C<math>_4</math>F<math>_8</math> flow [sccm]
|18
|-
|H<math>_2</math> flow [sccm]
|7
|-
|Pressure [mTorr]
|8
|-
|Spacer settings [mm]
|0
|-
|}
 
 
{| border="2" cellspacing="2" cellpadding="3"
|-style="background:DarkGray; color:White"
!Typical results
!PolySi mask - ''tested spring. 2012 by bge@danchip''
|-
|Etch rate
|~0.43 µm/min
|-
|Selectivity
|1:24
|-
|SiO2 etch uniformity
|&plusmn;2.2% over a 100mm wafer
|-
|Profile [<sup>o</sup>]
|see images
|-
|Images
|[[/Images of AOEpsiB_2|See here]]
|-
|Comments
|Line width reduction is about 3µm when etching 13µm down. See the images to get more info on this
|-
|}
 
<br clear="all" />
 
=Etching of micro structures in Aluminum oxide=
''by Fredrik Stöhr''
 
Aluminum oxide (Al<sub>2</sub>O<sub>3</sub>, Alumina) can be etched with the standard recipe for silicon oxide etching. The parameters including the chuck temperature are identical to the recipe described above: '''SiO2_res'''. ''The etch is probably very physical and gives redeposition, so please consider using a Cl2 etch on the ICP metal instead (BGHE 2015-04-17)'' <br>
 
'''General Description'''<br>
:Process date: Summer 2014<br>
:Aluminum Oxide with a thickness of 50 nm has been deposited by atomic layer deposition using the respective standard recipe.<br>
:Substrates: Blank 525 µm Silicon wafers or Silicon wafers with thermally grown Silicon Oxide prior to Alumina deposition. <br>
:Mask: [XOP8] AZ5214E 1.5 µm thick (HMDS pretreatment, 6-inch aligner 3 sec exposure, 60 sec development).
:Etch Load (Total Exposed SiO2): ~ 5 %<br>
:Post process: O2 Plasma Ashing 10 min


{| border="1" cellspacing="1" cellpadding="1" align="middle"
It has also been tested etching SiO2 layer on silicon wafers:  
![[image:FRSTO Al2O3 AOE 1 Top 05.jpg|300x300px|thumb|left|
*[[/With Hard Mask|SiO2 etching with hard mask]]
Etch time: 3 min. Substrate: Blank Si. <br>
Bird View. The dark area is Silicon. The bright area is Alumina. The black flakes stem from redeposited sputtered material and is most likely aluminum oxide, since it is almost non-volatile in the used plasma chemistry. It must have been laying on top of the photo resist mask and landed on the alumina after resist ashing.
]]
![[image:FRSTO Al2O3 AOE 2 Top 04.jpg|300x300px|thumb|left|
Etch time: 3 min. Substrate: Blank Si. <br>
Bird View. Close-up. The dark area is Silicon. The bright area is Alumina. The black flakes stem from redeposited sputtered material.
]]
![[image:FRSTO Al2O3 AOE 3 Top Tilt30 08.jpg|300x300px|thumb|left|
Etch time: 3 min. Substrate: Blank Si. <br>
Bird View. Close-up. The dark area is Silicon. The bright area is Alumina.
]]
![[image:FRSTO Al2O3 AOE 4 Cross06.jpg|300x300px|thumb|left|
Etch time: 3 min<br>
Cross section of deep reactive ion etched silicon (DRIE Pegasus), where the structured alumina was used as a mask. Remarkably, the etch selectivity of Alumina to Silicon is >1:10000.
]]
|-
|}
{| border="1" cellspacing="1" cellpadding="1" align="middle"
![[image:FRSTO Al2O3 AOE 5 Top Tilt30 05.jpg|300x300px|thumb|left|
Etch time: 10 min. Substrate: Blank Si. <br>
The view tilt angle is 30°. The edge is corrugated, which is most likely to the corrugated resist mask.
]]
![[image:FRSTO Al2O3 AOE 6 Top Tilt30 04.jpg|300x300px|thumb|left|
Etch time: 10 min. Substrate: Blank Si. <br>
The view tilt angle is 30°. Vertical striations and considerable over-etching of the Silicon substrate are apparent. It seems as if less material has been redeposited, which may be due to the prolonged etch time in comparison to the above.
]]
![[image:FRSTO Al2O3 AOE 7 Top Tilt30 01.jpg|300x300px|thumb|left|
Etch time: 10 min. Substrate: Blank Si. <br>
The view tilt angle is 30°. Vertical striations and considerable over-etching of the Silicon substrate are apparent. It seems as if less material has been redeposited, which may be due to the prolonged etch time in comparison to the above.
]]
|-
|}
{| border="1" cellspacing="1" cellpadding="1" align="middle"
![[image:FRSTO Al2O3 AOE 8 AOE15min Top Tilt45 21.jpg|300x300px|thumb|left|
Etch time: 15 min. Substrate: Silicon with 1 µm thermally grown SiO2 <br>
The view tilt angle is 45°. Alumina and Silicon Oxide may be etched in one go.
]]
![[image:FRSTO Al2O3 AOE 9 AOE15min Top Tilt45 27.jpg|300x300px|thumb|left|
Etch time: 15 min. Substrate: Silicon with 1 µm thermally grown SiO2 <br>
The view tilt angle is 45°. Alumina and Silicon Oxide may be etched in one go. Considerable over-etchign of the Silicon substrate is apparent.
]]
![[image:FRSTO Al2O3 AOE 10 AOE15min Top Tilt45 31.jpg|300x300px|thumb|left|
Etch time: 15 min. Substrate: Silicon with 1 µm thermally grown SiO2 <br>
The view tilt angle is 45°. Alumina and Silicon Oxide may be etched in one go. Considerable over-etchign of the Silicon substrate is apparent.
]]
|-
|}
<br clear="all" />


=Limitations using the AOE=
=Limitations using the AOE=
Line 482: Line 181:
!Typical results
!Typical results
!Si mask non-confirmed result
!Si mask non-confirmed result
!Si mask DANCHIP result
!Si mask Nanolab result
!Resist mask non-confirmed result
!Resist mask non-confirmed result
!Resist mask DANCHIP result
!Resist mask Nanolab result
|-
|-
|Etch rate [nm/min]
|Etch rate [nm/min]
Line 542: Line 241:
!Typical results
!Typical results
!Al mask non-confirmed result
!Al mask non-confirmed result
!Al mask DANCHIP result
!Al mask Nanolab result
|-
|-
|Etch rate [nm/min]
|Etch rate [nm/min]
Line 612: Line 311:
!Typical results
!Typical results
!Si mask non-confirmed result
!Si mask non-confirmed result
!Si mask DANCHIP result
!Si mask Nanolab result
!Al mask non-confirmed result
!Al mask non-confirmed result
!Al mask DANCHIP result
!Al mask Nanolab result
!Thin Al mask non-confirmed result
!Thin Al mask non-confirmed result
!Thin Al mask DANCHIP result
!Thin Al mask Nanolab result
|-
|-
|Etch rate [nm/min]
|Etch rate [nm/min]
Line 680: Line 379:
{| border="2" cellspacing="2" cellpadding="3"
{| border="2" cellspacing="2" cellpadding="3"
!Tested once
!Tested once
!Si mask DANCHIP result
!Si mask Nanolab result
|-
|-
|Etch rate [nm/min]
|Etch rate [nm/min]

Latest revision as of 17:38, 1 February 2023

Feedback to this page: click here

Click here to go to the AOE equipment page

This page is written by Berit Herstrøm @ DTU Nanolab (BGHE) if nothing else is stated

What masking material should I choose when etching SiO2/glass in the AOE?

Photoresist mask - not too deep etches
Etching SiO2 with resist as masking material is the prefered masking material for many purposes. The main reason for using photo resist as masking material is that it is easy and fast to make and easy to remove afterwards. The selectivity of resist to SiO2 is in the range of 2-4.

The main draw back when using photoresist as masking material is heating of the substrate during the etch. SiO2 is a hard material to etch and therefore needs a high DC bias to allow the ion bombardment to be enegetic enough to etch the SiO2. This ion bombardment heats up the surface and even when cooling the platen to zero degrees Celcius the resist mask can exceed 100 degrees Celcius. Combined with the fact that the plasma UV hardens the surface of the resist this can create crumpled resist surface and perforated egdes, see images here. Etching a few microns down in the SiO2 normally does not heat up the resist too much but when etching deeper like 5-10µm there is a large change for getting problems with overheating the resist.


Si/P-Si mask - deeper etches
P-Si is a good masking layer for deeper etches. The selectivity to SiO2 is measured to be better than 1:15. The P-Si on the back side seems to prevent declamping of a APOX (thick oxide) substrate during a deep etch on a high load wafer (e.g. 50% load), contrary to using photoresist mask on the APOX substrate. The wafer bow is created when removing part of the top oxide layer due to stress in the oxide layers.

Drawbacks: the recipe we have now is giving a high line width reduction (1µm when etching 7.5µm down). There is tendency for silicon masks to sputter at an angle near 45 degrees, so even if it seems like there is enough Si mask on top this will given mask recession at the edges and lead to an angled sidewall profile. Take a look at some recipes and results


Al mask - deeper etches - more redeposition

Al is allowed as masking material but we do not advise it. It can however be useful under some circumstances. It is expected to have a high selectivity to SiO2 greater than 50.

Draw back: The drawback is that Al does not form any volatile products with the Flour gasses. This means that any Al sputtered of has the chance of getting redeposited on the surface. AlF3 sputters of very easily.


Cr mask - deeper etches/high aspect ratio etches where the other materials cannot be used

Cr works well as masking material but due to cross contamination issues we prefer to avoid Cr in the machine. Cr does in contrary to Al form some volatile components with the flour gasses and therefore redeposition problems are not so severe. We do allow Cr as masking material when the other masking materials cannot be used.

So fare it has been found useful for etching nanostructures in quartz substrates and has briefly been tested in etching of fused silica. Etching with flour gasses and small amount of O2 Cr seems to etch well, so for high selectivity you must avoid small amounts of O2 in the recipe.


QC on the AOE

Quality Control (QC) for AOE
QC Recipe: QC mres
C4F8 flow 5 sccm
H2 flow 4 sccm
He flow 174 sccm
Pressure 4 mTorr
Coil power 1300 W
Platen power 200 W
Platen Temperature 20 deg. C
Etch Load 100%
QC limits AOE
Etch rate in SiO2 180 - 195 nm/min
Non-uniformity <2.28 %


Standard silicon oxide etch using resist as masking material

Etching of micro structures in Silicon Oxide with PolySi as masking material

The choice of recipe depends on your preferences. Some different etch recipes are given here. These are all variations over the same recipe so the differences are minor. You can choose between getting:


Etching SiO2 with hard mask (metal or dielectrics)

So fare it has been found useful for

and has briefly been tested in

It has also been tested etching SiO2 layer on silicon wafers:

Limitations using the AOE

Wafer bow

There is a limit to how much the wafer can bow and still be clamped on the chuck. The limit can maybe vary a little over time and may also depend on the material on the backside of the substrate. On a 100mm Si wafer with SiO2 on the backside (<10µm) we expect the limit to be around 50µm bow (when the back side surface is convex).

A bow will be created when etching the top oxide layer on a wafer with oxide on both sides. For a larger etch load the bow will be more severe for a specific etch depth when for a smaller etch load. I have been able to etch much deeper in SiO2 with a P-Si mask than with a photo resist mask on a wafer with 50% load. When using photoresist the wafer stopped clamping during the etch after just a few µm. With P-Si I could etch 15µm without problems. I expect this to be due to a combination of P-Si on the back side clamping much better and P-Si on the back side helping to reduce the bow.


Transparent wafers

Transparent wafers are a challange for two reasons. 1. In the load lock the LASER detection system that is used to detect the wafer during mapping cannot detect a completely transparent wafer. 2. A transparent wafer is either quartz or fused silicon. These materials are very difficult to clamp electrostatically and will therefore not be able to pass the He leak up test succesfully.

  1. The first issue may be overcome by using a non-transparent masking material or adding a non-transparent material on the back side of the wafer (could be aluminium).
  2. The second issue may be overcome by reducing the He back side pressure or reducing the He back side cooling completely. Another way to solve it is to either bond the transparent wafer to a silicon wafer before transfering it into chamber or deposite a more conducting layer on the backside of the wafer. This could be aluminium but also 1-2µm P-Si may be enough.






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