Specific Process Knowledge/Thin film deposition/Deposition of Gold: Difference between revisions

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Gold can be deposited by e-beam evaporation or sputtering. In the chart below you can compare the different deposition equipment.
Gold can be deposited by e-beam evaporation or sputtering. In the chart below you can compare the different deposition equipment.
== Adhesion of Au on Si ==
The adhesion of Au on Si is not very good, and an adhesionlayer is often deposited on the wafer, before the Au layer evaporated. A good metal to use as adhesionlayer is Ti, but Cr is also often used.
The most commonly used thickness of the Ti adhesionlayer is 10 nm. Also thinner layers, for example 5 nm, can be used.




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'''*'''  ''For thicknesses above 200 nm permission from ThinFilm group (thinfilm@danchip.dtu.dk) is required.''
'''*'''  ''For thicknesses above 200 nm permission from ThinFilm group (thinfilm@danchip.dtu.dk) is required.''
== Adhesion of Au on Si ==
[[/Adhesion of Au|Adhesion of Au layers]]


== Studies of Au deposition processes in the Wordentec==
== Studies of Au deposition processes in the Wordentec==

Revision as of 11:03, 12 February 2016

4th Level - Comparison

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Gold can be deposited by e-beam evaporation or sputtering. In the chart below you can compare the different deposition equipment.


Adhesion of Au on Si

The adhesion of Au on Si is not very good, and an adhesionlayer is often deposited on the wafer, before the Au layer evaporated. A good metal to use as adhesionlayer is Ti, but Cr is also often used. The most commonly used thickness of the Ti adhesionlayer is 10 nm. Also thinner layers, for example 5 nm, can be used.


E-beam evaporation (Alcatel) E-beam evaporation (Wordentec) Sputter (Lesker) E-beam evaporation (Physimeca) Sputter coater Hummer Sputter coater Balzer
General description E-beam deposition of Au E-beam deposition of Au Sputter deposition of Au E-beam deposition of Au Sputter deposition of Au Sputter deposition of Au
Pre-clean RF Ar clean RF Ar clean RF Ar clean
Layer thickness 10 Å to 5000Å* 10 Å to 5000Å* 10 Å to 10Å to about 3000Å*
Deposition rate 2 Å/s to 10 Å/s 1 Å/s to 10 Å/s From 5 Å/s up to 10Å/s Not measured Not measured
Batch size
  • Up to 1x4" wafers
  • smaller pieces
  • 24x2" wafers or
  • 6x4" wafers or
  • 6x6" wafers
  • Pieces or
  • 1x4" wafer or
  • 1x6" wafer
  • 1x 2" wafer or
  • 1x 4" wafers or
  • Several smaller pieces
  • 1x4" wafer
  • Several smaller samples
  • 1 large sample (< 4" wafer)
  • Several smaller samples
Allowed materials
  • Silicon oxide
  • Silicon (oxy)nitride
  • Photoresist
  • PMMA
  • Mylar
  • SU-8
  • Metals
  • Silicon oxide
  • Silicon (oxy)nitride
  • Photoresist
  • PMMA
  • Mylar
  • SU-8
  • Metals
  • Silicon
  • Silicon oxide
  • Silicon nitride
  • Silicon (oxy)nitride
  • Photoresist
  • PMMA
  • Mylar
  • SU-8
  • Metals
  • Carbon
  • III-V materials
  • Silicon wafers
  • Quartz wafers
  • Pyrex wafers
. .


Comment
  • For thicknesses above 200 nm permission is required
  • An adhesion layer (of Cr or Ti) is recommended under Au.
  • For thicknesses above 200 nm permission is required
  • An adhesion layer (of Cr or Ti) is recommended under Au.
Used to gold sputter coating of

samples mainly before SEM characterization

Used to gold sputter coating of

samples mainly before SEM characterization


* For thicknesses above 200 nm permission from ThinFilm group (thinfilm@danchip.dtu.dk) is required.

Studies of Au deposition processes in the Wordentec

Roughness of Au layers - Roughness of Au layers deposited with different equipment and settings

Wafer temperature

The wafer temperature during e-beam deposition of 200 nm Au on six wafers has been measured using thermal labels on the backside of the wafers. The following results were obtained:

Wafer Temperature [C]
1 48
2 60
3 65
4 71
5 71
6 77

The temperatures are accurate within approximately +/- 3C and probably underestimating the actual wafer temperature slightly. It is observed that the wafer temperature increases with each wafer, thus if wafer temperature is of concern it is advised to reduce the number of wafers per run.