View source for LabAdviser/Introduction to LabAdviser and Processing/Solar cell process flow

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===Introduction===

[[image:Solar cell.jpg|450x450px|left|thumb|Figure 1. A wafer with an array of solar cells.]]

===What does it at minimum take to make a solar cell?===


If we take a look at the cross section of a simple silicon based solar cell (eg. between two fingers on figure 1) we see a structure as shown on figure 2. The solar cell consists of an '''absorber''' (p-doped bulk silicon crystal), an '''electron membrane''' (shallow n-doped layer on top of the silicon crystal) and '''metal contacts'''.

When shining light on the solar cell photons will be absorbed and electron-hole pairs will be generated in the crystal. Electron-hole pairs generated near the p-n junction will contribute to a current flowing from the p- to the n-doped region. Negative charge carriers will move towards the n-doped region while positive charge carriers will move away from the n-doped region. In order to use the generated electricity the cell has to be placed in a circuit such that electrons can flow freely and continuously from the n-doped region to the p doped region through a load (for instance a light bulb). To ease the flow of electrons '''metal contacts''' are made on each side of the cell. When the electrons reach the p-doped region through the backside contact they will recombine with the holes. To minimize the reflectance of the incoming light on the surface (and thereby harvesting more energy from the light source to contribute to the generation of electron-hole pairs), an '''anti-reflecting coating''' can be deposited on the front side of the cell.

[[image:Solarcell2.jpg|550x550px|left|thumb|Figure 2. Cross section of the solar cell.]]
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===How to fabricate solar cells===

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To process silicon based solar cells as shown we have to make a process recipe with all the steps in the right order. A general rule of processing is that all high temperature processes come as early as possible and low temperature processes and metal steps come as late as possible. 

Since '''oxide growth''' and '''doping by diffusion''' are high temperature processes we start making the '''n-doped''' layer and '''anti-reflecting coating layer'''. This is done by first growing an oxide and then by photo-lithography define the areas that must be n-doped. The oxide is etched and the doping carried out. Next, the anti-reflecting coating is made by growing an oxide of a specific thickness. 

To make the contacts we first have to define the areas where contact to the n-doped layer on the front side is needed. This is also done by a lithographic step followed by an oxide etch, which removes the oxide on the back side as well. 

Finally, a photo-lithographic step is carried out to define the shape of the contacts and interconnections on the front side. This is done by using a negative photoresist that allows for a '''metal lift-off process'''. Metal is evaporated on the defined resist pattern on the front side as well as on the backside forming the '''contact anode'''. The resist is subsequently removed (lifted) in acetone together with the excess metal only leaving metal at the defined areas and at the backside.

The performance of the solar cell can be optimized by adding a high p-doping on the backside of the wafer. At which point in the process should you do add this step?
Several initiates can also be made in order to increase the amount of energy that will contribute to the process by adding more sophisticated anti-reflecting coatings as well as structuring the front side such that it is more likely that the incoming light is captured and absorbed in the cell. 

Beneath you can see an example of a process recipe with all process steps needed to fabricate a wafer with solar cells. In the process you will find links to the actual machines and processes described in LabAdviser, where you can get more detailed information. Before doing the processing you also have to find the right processing parameters, they are not listed here.

[[image:9 Lift-off.jpg|550x550px|left|thumb|Figure 3. Cross section of the clean room fabricated solar cell.]]
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A more detailed process flow for the solar cell process flow, including all steps and process parameters, can be found here:

[[file:Green_Belt_Jan_2013_Process.docx |Process flow for the solar cell fabrication process]] or as pdf
[[media:GGreen_Belt_Jan_2013_Process.pdf |Process flow for the solar cell fabrication process (PDF)]]

==Process flow==

''This is a sketchy description of how a solar cell can be fabricated (some details are omitted).  ''
[[image:Color_explanations.JPG|130x130px|center|]]

===1 Thermal oxidation===

<!--[[image:1 Thermal oxidation.jpg|350x350px|left|thumb|]]-->

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!colspan="2" border="none" style="background:#6495ED; color:black;" align="center" width="225px"|Step
!width="250px" style="background:#6495ED; color:black"|Description
!width="200px" style="background:#6495ED; color:black"|LabAdviser link
!width="260px" style="background:#6495ED; color:black"|Image showing the step
|-

|-
!1.1
|Si wafer
|Start with a 100 mm Si<100> wafer that is single side polished and p doped with boron. This will be the '''absorber''' in the final solar cell.
|[[Specific_Process_Knowledge/Wafer_Information|Wafer information]], types of avaliable wafers are listed.
|[[image:1 Si wafer.jpg|250x350px|center|]]
|-

|- style="background:#BCD4E6; color:black"
!1.2
|RCA clean
|The wafer has to be RCA cleaned, before entering an oxidation furnace.
|[[Specific_Process_Knowledge/Wafer_cleaning/RCA|RCA cleaning]], the different steps in the cleaning procedure are described.
|&nbsp;
|-

|- 
!1.3
|SiO<sub>2</sub> dry oxidation
|Grow a dry thermal oxide layer in the Boron Drive-in furnace (A1). The oxide layer will be patterned later on to define '''n-doped''' areas ("'''electron membrane'''".)
|[[Specific_Process_Knowledge/Thermal_Process/A1_Bor_Drive-in_furnace|Boron Drive-in furnace]], info about performance and process parameter range.
||[[image:1_3_oxide.JPG|250x350px|center|]]
|-
|-
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===2 Lithography and oxide etch===

<!--[[image:2 Lithography and oxide etch.jpg|350x350px|left|thumb|]]-->

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!colspan="2" border="none" style="background:#6495ED; color:black;" align="center" width="225px"|Step
!width="250px" style="background:#6495ED; color:black"|Description
!width="200px" style="background:#6495ED; color:black"|LabAdviser link
!width="260px" style="background:#6495ED; color:black"|Image showing the step
|-

|-
!2.1
|HMDS surface treatment
|To ensure the resist sticks to the surface, the wafer is HMDS treated before resist spinning.
|[[Specific_Process_Knowledge/Photolithography/Pretreatment#HMDS|HMDS oven]]
|&nbsp;
|-

|-
|- style="background:#BCD4E6; color:black"
!2.2
|Spin resist on wafer backside 
|The backside of the wafer needs to be protected, to prevent the SiO<sub>2</sub> from being etched in the first etch step (section 3).
|[[Specific_Process_Knowledge/Photolithography/Photoresist_Spinners#Maximus|Resist spinners]]. Information about what resists that can be used with the spinners.
|[[image:1 Resist back.jpg|250x350px|center|]]
|-

|-
!2.3
|Spin resist on wafer frontside
|The frontside of the wafer is covered with a resist layer. 
|Information about resist processing, [[Specific_Process_Knowledge/Photolithography/AZ5214E_standard_resist_-_positive_process|positive]] and [[Specific_Process_Knowledge/Photolithography/AZ5214E_standard_resist_-_reverse_process|reversed]] lithography processes.
|[[image:1 Resist front.jpg|250x350px|center|]]
|-

|-
|- style="background:#BCD4E6; color:black"
!2.4
|Expose photoresist in aligner
|The resist layer on the wafer frontside is exposed in the aligner, with a dark field mask. Align the mask to wafer flat, and use hard contact.
|[[Specific_Process_Knowledge/Photolithography/Exposure_-_mask_aligner#Aligner-6inch_-EVG620|Aligner-6inch - EVG620.]] Here you can see a comparison between different aligners.
|[[image:2 lithography mask 1.jpg|250x350px|center]]
|-

|-
!2.5
|Develop photoresist 
|In the development step the '''exposed resist is removed,''' so that a resist pattern is formed on the surface.
|[[Specific Process Knowledge/Lithography/Development|Development,]] standard development times are listed.
|[[image:1 Lithography.jpg|250x350px|center]]
|-


|-
|- style="background:#BCD4E6; color:black"
!2.6
|Optical microscope inspection
|Check the results of the exposure and development with an optical microscope by inspecting that the pattern and alignment marks are clearly visible. Right image: top view of alignment marks. The alignment marks will be used to align the wafer to the mask in next lithography step (section 5).
||The different [[Specific_Process_Knowledge/Characterization/Optical_microscope| optical microscopes]] and their features are listed.
 |[[image:mask1_SiO-etch-2.jpg|150x150px|center]]
|-


|-
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===3 SiO<sub>2</sub> etch===

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!width="250px" style="background:#6495ED; color:black"|Description
!width="200px" style="background:#6495ED; color:black"|LabAdviser link
!width="260px" style="background:#6495ED; color:black"|Image showing the step
|-

|-
|-
!3.1
|SiO<sub>2</sub> etch
| Etch through the SiO<sub>2</sub> layer, where the resist is not covering the SiO<sub>2</sub>, using Sioetch. Sioetch is BHF with a surfactant.
|[[Specific_Process_Knowledge/Etch/Wet_Silicon_Oxide_Etch_(BHF)|Wet silicon oxide etch (BHF)]]. Etch rates for BHF and HF etches are listed for oxides deposited with different methods. 
|[[image:3_1_oxide_etch.JPG|250x350px|center]]
|-

|-
|- style="background:#BCD4E6; color:black" 
!3.2
|Inspection
|Inspect the pattern and alignment marks with an optical microscope to check the result of the SiO<sub>2</sub> etch.
|The different [[Specific_Process_Knowledge/Characterization/Optical_microscope|optical microscopes]] and their features are listed.
|&nbsp;
|-

|-
!3.3
|Strip resist
|The resist is removed with acetone. First 2-3 min in rough followed by 5 min in fine strip bath with ultrasound.
|[[Specific_Process_Knowledge/Photolithography/Stripping_equipment#Acetone_strip_with_ultrasound|Acetone strip with ultrasound.]]
|[[image:3_3_resist_strip.JPG|250x350px|center]]
|-
|-

|}

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===4 Phosphorous doping===

<!--[[image:3 Phosphor doping.jpg|350x350px|left|thumb|]]-->


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!width="250px" style="background:#6495ED; color:black"|Description
!width="200px" style="background:#6495ED; color:black"|LabAdviser link
!width="260px" style="background:#6495ED; color:black"|Image showing the step
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|-
|- 
!4.1
|RCA cleaning 	
|The wafer has to be RCA cleaned, before entering a pre-deposition furnace. Skip the HF dip to prevent that some of the oxide is removed.
|[[Specific_Process_Knowledge/Wafer_cleaning/RCA|RCA cleaning]], the different steps in the cleaning procedure are described.
|&nbsp;
|-

|- style="background:#BCD4E6; color:black"
!4.2
|Phosphorus pre-deposition
|Areas that should be '''n-doped''' have been defined by photolithography and etched, and in this step these areas are '''doped by diffusion''' in the Phosphorus Pre-dep furnace.
|[[Specific_Process_Knowledge/Thermal_Process/A4_Phosphor_Pre-dep_furnace|Phosphorus Pre-dep furnace (POCL)]]. Here information about process temperatures and gasses are found. 
|[[image:Step 4.2.jpg|250x350px|center]]
|-

|-
|- 
!4.3
|Etch of phosphorus glass
|All phosphorus glass and only some of the dry oxide is removed in this step by a BHF etch in the RCA bench for doped wafers.
|[[Specific_Process_Knowledge/Etch/Wet_Silicon_Oxide_Etch_%28BHF%29|BHF etch]].
|&nbsp;
|-




|- style="background:#BCD4E6; color:black"
!4.4
|SiO<sub>2</sub> dry oxidation
|An '''anti reflective coating''' is made by an oxide growth (of a specific thickness).
|[[Specific_Process_Knowledge/Thermal_Process/A3_Phosphor_Drive-in_furnace|Phosphorous Drive-in furnace]] with information about performance and allowed substrates.
|[[image:4_4_oxidation.JPG|250x350px|center]]
|-

|-
|- 

|-
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===5 Lithography – 1.5µm standard===

<!--[[image:2 Lithography and oxide etch.jpg|350x350px|left|thumb|]]-->

<!--[[image:1 Thermal oxidation.jpg|350x350px|left|thumb|]]-->


{| border="1" cellspacing="1" cellpadding="3" style="text-align: left; width: 925px; height: 220px;"
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|-
!colspan="2" border="none" style="background:#6495ED; color:black;" align="center" width="225px"|Step
!width="250px" style="background:#6495ED; color:black"|Description
!width="200px" style="background:#6495ED; color:black"|LabAdviser link
!width="260px" style="background:#6495ED; color:black"|Image showing the step
|-

|-
!5.1
|HMDS surface treatment
|To ensure the resist sticks to the surface, the wafer is HMDS treated before resist spinning.
|[[Specific_Process_Knowledge/Photolithography/Pretreatment#HMDS|HMDS oven]]
|&nbsp;
|-

|-
|- style="background:#BCD4E6; color:black"
!5.2
|Spin resist on wafer frontside
|The frontside of the wafer is covered with a resist layer
|[[Specific_Process_Knowledge/Photolithography/Photoresist_Spinners#Maximus|SSE spinner]] 
|[[image:5_2_resist_spinning.JPG|250x350px|center]]
|-

|-
!5.3
|Expose photoresist in aligner
|The wafer needs to be aligned to the mask.  "Hard contact" is recommended.
|[[Specific_Process_Knowledge/Photolithography/Exposure_-_mask_aligner#Aligner-6inch_- EVG620|Aligner-6inch -EVG620]]. Here you can see a comparison between different aligners.
|[[image:5 lithography mask 2.jpg|250x350px|center]]
|-

|- style="background:#BCD4E6; color:black"
!5.4
|Develop photoresist 
|In the development step the '''exposed resist is removed,''' and a resist pattern is formed on the surface.
|[[Specific Process Knowledge/Lithography/Development|Development]]
|[[image:5_4_development.JPG|250x350px|center]]
|-

|-
|- 
!5.5
|Optical microscope inspection
|Check the pattern and alignment marks with an optical microscope. The alignment marks should be aligned to the marks from the previous lithography step (section 2). Right image: top view of alignment marks after second lithography step.
||The different [[Specific_Process_Knowledge/Characterization/Optical_microscope|optical microscopes]] and their features are listed.
 |[[image:Alignment_marks_2.jpg|150x150px|center]]
|-

|-
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===6 SiO<sub>2</sub> etch===


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|-
!colspan="2" border="none" style="background:#6495ED; color:black;" align="center" width="225px"|Step
!width="250px" style="background:#6495ED; color:black"|Description
!width="200px" style="background:#6495ED; color:black"|LabAdviser link
!width="260px" style="background:#6495ED; color:black"|Image showing the step
|-

|-
|-
!6.1
|SiO<sub>2</sub> etch
|Remove oxide with Sioetch in the areas where the '''metallic contact (cathodes''') will be placed (section 8). Sioetch is BHF with a surfactant.  
|[[Specific_Process_Knowledge/Etch/Wet_Silicon_Oxide_Etch_(BHF)|Wet Silicon Oxide Etch (BHF)]]. Etch rates for BHF and HF etches are listed for oxides deposited with different methods. 
|[[image:6_1_oxide_etch.JPG|250x350px|center]]
|-

|-
|- style="background:#BCD4E6; color:black"
!6.2
|Optical microscope inspection
|Inspect the pattern and alignment marks with an optical microscopes to check the result of the lithography step. The alignment marks should be clearly visible.
|The different [[Specific_Process_Knowledge/Characterization/Optical_microscope|optical microscopes]] and their features are listed. 
|&nbsp;
|-

|-
!6.3
|Strip resist
|The resist is removed with acetone. First 2-3 min in rough followed by 5 min in fine strip bath with ultrasound.
|[[Specific_Process_Knowledge/Photolithography/Stripping_equipment#Acetone_strip_with_ultrasound|Acetone strip with ultrasound.]]
|[[image:6_3_strip_resist.JPG|250x350px|center]]
|-
|-

|-
|- style="background:#BCD4E6; color:black"
!6.4
|Stylus profiler inspection
|The step height of the SiO<sub>2</sub> in the doped and undoped areas are measured after the SiO<sub>2</sub> etch.
|[[Specific Process Knowledge/Characterization/Profiler|Stylus profilers]]. The different stylus profilers and their features are described. 
|&nbsp;
|-

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===7 Lithography - 2.2 µm  image reversal===


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|-
!colspan="2" border="none" style="background:#6495ED; color:black;" align="center" width="225px"|Step
!width="250px" style="background:#6495ED; color:black"|Description
!width="200px" style="background:#6495ED; color:black"|LabAdviser link
!width="260px" style="background:#6495ED; color:black"|Image showing the step
|-

|-
!7.1
|HMDS surface treatment
|To ensure the resist sticks to the surface, the wafer is HMDS treated before resist spinning. 
|[[Specific_Process_Knowledge/Photolithography/Pretreatment#HMDS|HMDS oven]]
|&nbsp;
|-

|-
|- style="background:#BCD4E6; color:black"
!7.2
|Spin resist on wafer frontside 	
|The frontside of the wafer is covered with a resist layer. 
|[[Specific_Process_Knowledge/Photolithography/Photoresist_Spinners#Maximus|Spinners]], information about what resists that can be used with the spinners.
|[[image:7_2_spin_resist.JPG|250x350px|center]]
|-

|-
!7.3
|Expose photoresist in aligner 
|The resist is exposed in an aligner, with a bright field mask. The alignment marks on the wafer need to be aligned to the marks on the mask. "Hard contact" is recommended.
|Details on [[Specific_Process_Knowledge/Photolithography/Making_Mask_design#Alignment_marks|alignment marks]] (if you would design a mask).
|[[image:7 lithography mask 3.jpg|250x350px|center]]
|-

|- style="background:#BCD4E6; color:black"
!7.4
|Reversed bake
|To do a reversed process the wafer is heated up. 
|[[Specific_Process_Knowledge/Photolithography/AZ5214E_standard_resist_-_reverse_process|Reversed]] photolithography process.
|[[image:7 4 Reversed bake.jpg|250x350px|center]]
|-

|-
!7.5
|Flood exposure
|The entire wafer is exposed without a mask.
|[[Specific_Process_Knowledge/Photolithography/Photolithography_guide|The most used photolithography process flows]], describing the steps in the lithography process.
|[[image:Reversal litho 7.5.jpg|250x350px|center]]
|-

|- style="background:#BCD4E6; color:black"
!7.6
|Develop photoresist 
|The '''non-exposed resist''' is removed, so that a resist pattern is formed on the surface. The resist has negative sloped side walls after a revered photolithography step, which is good for lift-off.
|[[Specific Process Knowledge/Lithography/Development|Development]]
|[[image:7 6 develop resist.JPG|250x350px|center]]
|-

|- 
!7.7
|Optical microscope inspection
|Check the pattern and alignment marks with an optical microscope. The alignment marks should be aligned to the marks from the two previous lithography steps (section 2 and 5). Right image: alignment marks after the third lithography step.
||The different [[Specific_Process_Knowledge/Characterization/Optical_microscope|optical microscopes]] and their features are listed.
 |[[image:mask3- liftoff.jpg|150x150px|center]]
|-

|-
|}
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===8 Aluminium pattern===


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!colspan="2" border="none" style="background:#6495ED; color:black;" align="center" width="225px"|Step
!width="250px" style="background:#6495ED; color:black"|Description
!width="200px" style="background:#6495ED; color:black"|LabAdviser link
!width="260px" style="background:#6495ED; color:black"|Image showing the step
|-

|-
!8.1 
|Aluminium deposition on wafer frontside
|Deposit metal on the wafer frontside to fabricate contacts ('''contact cathodes'''). || [[Specific_Process_Knowledge/Thin_film_deposition/Alcatel|Alcatel,]] materials can be deposited in this deposition tool.    ||[[image:8_1_metal_on_frontside.JPG|250x350px|center]]
|-

|- style="background:#BCD4E6; color:black"
!8.2
|Aluminium deposition on wafer backside
|Deposit metal for contacts ('''contact anode''') on the wafer backside. || [[Specific_Process_Knowledge/Thin_film_deposition/Deposition_of_Aluminium|Deposition of Aluminum]] can be done with several machines in the cleanroom.   || [[image:8_2_after_metal_before_lift.JPG|250x350px|center]]
|-

|-
!8.3
|Lift-off
|Remove the resist and the metal deposited on top of the areas covered by resist.
| [[Specific_Process_Knowledge/Photolithography/Stripping_equipment#Lift-off_wet_bench|Lift off bench]]
|[[image:8_3_lift_off.JPG|250x350px|center]]
|-

|- style="background:#BCD4E6; color:black"
!8.4
|Optical microscope inspection
|Check the final result with an optical microscope.
|[[Specific_Process_Knowledge/Characterization/Optical_microscope|Optical microscopes]] 
|&nbsp;
|-

|-color:black"
!8.5
|Stylus profiler inspection
|Check the final result by measuring the profile of the aluminium structures on the wafer frontside with a stylus profilometer.
|[[Specific Process Knowledge/Characterization/Profiler|Stylus profilers]]
|[[image: Profile_After_lift_off_solar cell.JPG|250x350px|center]]
|-

|- style="background:#BCD4E6; color:black"
!8.6
|4 point probe inspection
|Measure the metal sheet resistance on the wafer backside with a 4 point probe.
|[[Specific_Process_Knowledge/Characterization/4-Point_Probe|4 point probe]] 
|&nbsp;
|-

|-
|}

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