View source for LabAdviser/Technology Research/Presentation Form/Process flow form

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!colspan="2" border="none" style="background:#6495ED; color:black;" align="center" width="225px"|Step
!width="250px" style="background:#6495ED; color:black"|Description
!width="200px" style="background:#6495ED; color:black"|LabAdviser link
!width="260px" style="background:#6495ED; color:black"|Image showing the step
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!1.1
|Si wafer
|Start with a 100 mm Si<100> wafer that is single side polished and p doped with boron. This will be the '''absorber''' in the final solar cell.
|[[Specific_Process_Knowledge/Wafer_Information|Wafer information]], types of avaliable wafers are listed.
|[[image:1 Si wafer.jpg|250x350px|center|]]
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!1.2
|RCA clean
|The wafer has to be RCA cleaned, before entering an oxidation furnace.
|[[Specific_Process_Knowledge/Wafer_cleaning/RCA|RCA cleaning]], the different steps in the cleaning procedure are described.
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!1.3
|SiO<sub>2</sub> dry oxidation
|Grow a dry thermal oxide layer in the Boron Drive-in furnace (A1). The oxide layer will be patterned later on to define '''n-doped''' areas ("'''electron membrane'''".)
|[[Specific_Process_Knowledge/Thermal_Process/A1_Bor_Drive-in_furnace|Boron Drive-in furnace]], info about performance and process parameter range.
||[[image:1_3_oxide.JPG|250x350px|center|]]
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===2 Lithography and oxide etch===

<!--[[image:2 Lithography and oxide etch.jpg|350x350px|left|thumb|]]-->

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!colspan="2" border="none" style="background:#6495ED; color:black;" align="center" width="225px"|Step
!width="250px" style="background:#6495ED; color:black"|Description
!width="200px" style="background:#6495ED; color:black"|LabAdviser link
!width="260px" style="background:#6495ED; color:black"|Image showing the step
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!2.1
|HMDS surface treatment
|To ensure the resist sticks to the surface, the wafer is HMDS treated before resist spinning.
|[[Specific_Process_Knowledge/Photolithography/Pretreatment#HMDS|HMDS oven]]
|&nbsp;
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!2.2
|Spin resist on wafer backside 
|The backside of the wafer needs to be protected, to prevent the SiO<sub>2</sub> from being etched in the first etch step (section 3).
|[[Specific_Process_Knowledge/Photolithography/Photoresist_Spinners#Maximus|Resist spinners]]. Information about what resists that can be used with the spinners.
|[[image:1 Resist back.jpg|250x350px|center|]]
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!2.3
|Spin resist on wafer frontside
|The frontside of the wafer is covered with a resist layer. 
|Information about resist processing, [[Specific_Process_Knowledge/Photolithography/AZ5214E_standard_resist_-_positive_process|positive]] and [[Specific_Process_Knowledge/Photolithography/AZ5214E_standard_resist_-_reverse_process|reversed]] lithography processes.
|[[image:1 Resist front.jpg|250x350px|center|]]
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!2.4
|Expose photoresist in aligner
|The resist layer on the wafer frontside is exposed in the aligner, with a dark field mask. Align the mask to wafer flat, and use hard contact.
|[[Specific_Process_Knowledge/Photolithography/Exposure_-_mask_aligner#Aligner-6inch_-EVG620|Aligner-6inch - EVG620.]] Here you can see a comparison between different aligners.
|[[image:2 lithography mask 1.jpg|250x350px|center]]
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!2.5
|Develop photoresist 
|In the development step the '''exposed resist is removed,''' so that a resist pattern is formed on the surface.
|[[Specific Process Knowledge/Lithography/Development|Development,]] standard development times are listed.
|[[image:1 Lithography.jpg|250x350px|center]]
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!2.6
|Optical microscope inspection
|Check the results of the exposure and development with an optical microscope by inspecting that the pattern and alignment marks are clearly visible. Right image: top view of alignment marks. The alignment marks will be used to align the wafer to the mask in next lithography step (section 5).
||The different [[Specific_Process_Knowledge/Characterization/Optical_microscope| optical microscopes]] and their features are listed.
 |[[image:mask1_SiO-etch-2.jpg|150x150px|center]]
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