LabAdviser/Technology Research/Technology Development of Nanoscale Silicon Plasma Etching Process
Technology Development of Nanoscale Silicon Plasma Etching process for Novel Devices and Applications
- Project type: Ph.D. project
- Project responsible: Vy Thi Hoang Nguyen
- Supervisors:Henri Jansen, Flemming Jensen, Jörg Hübner
- Partners involved: DTU Nanolab
Project Description
Plasma processes are important for silicon-based micro electromechanical systems (MEMS) with critical dimensions around a few microns. With the lithographic tools pushing the limits further down, also the dimensions of MEMS devices are rapidly decreasing and commercial nano electromechanical systems (NEMS) are underway. Emerging applications include NEMS resonators and sensors for physical and bio-chemical sensing down to the molecular level both because of the much reduced mass, nanowires for novel transistors and photovoltaics increasingly exploring quantum effects starting at the sub-50nm level, nanostructures for photonics (around the wavelength of the guided photons) and next generation storage (10nm and below), black silicon for large area catalysed reaction chambers and photovoltaics, through wafer vias for packaging applications, and nano imprint lithography (NIL) masters. Furthermore, instead of silicon, diamond is increasingly important as a structural material because of its remarkable properties such as electrical conductivity and hardness.
Typically all these devices have customized process flows but synergies can be found as most are produced using a 2.5D approach comprising sequential deposition, lithography and etch steps. The majority, such as accelerometers and gyroscopes, are based on sub-100 micron depth features with piezo-resistive transduction or submicron gap capacitive sensing. Trends are towards higher aspect ratio etches (depth/width>30) and small footprint devices for enhanced performance. Increasingly, large cavities (10-100 microns in width) are being etched for subsequent chip or wafer scale packaging and sensor structures may comprise multi-wafer stacks with one or more having through wafer etches (200-800 microns deep). High speed etching with excellent profiles control to facilitate e.g. copper feedthroughs is indispensable for such applications. For NIL applications, it is essential that the mold releases cleanly and a smooth sidewall without any negative profile that would prevent release.
Although widely utilized and largely understood, silicon etch processes fail to reproduce at the nanoscale. Transport effects ‘down the etched cavity’ limit rate and selectivity while aspect ratios, profile and passivation control are more challenging. For example, aspect ratios beyond 30 are rarely utilized and fluctuations in the results are common. So, at the nanoscale, etching becomes more difficult. Basically, two types of etching techniques can be distinguished; the continuous (or mixed) process and the alternating (or pulsed/Bosch) process. The continuous process generally has smooth sidewalls and low undercut and it is the standard technique in mainstream nano-electronic chip fabrication. However, at room temperature the mixed gas process, results in a low rate selectivity and aspect ratio capability – as such it is limited to shallow features. The alternating etch process is probably the most popular technique in MEMS production facilities today. It uses a repeating sequence of plasma enhanced deposition to passivate silicon features, a physical etch for directional removal of this layer at the base of the features, and an isotropic etch for silicon removal at the cleared surfaces. However, it is not well suited to the nanoscale due to finite sidewall scallop size and undercut unless rate and selectivity are severely compromised. Typically it is not applied below 500nm trench feature sizes – although 100nm features have been demonstrated.
The major part of this project will be related to experimental work in the cleanroom facility at DTU Danchip. It is the quest to develop a fundamental understanding of the special challenges involved in dry etching at the nanoscale including the physics and chemistry involved in the processing. The aim is to establish a generic knowledge platform for the nanoscale dry etching for future applications. An important part of the project will be to demonstrate the ability of 3D plasma etching technology in both micro- and nanoscale.
In this project, the usability of SF6 and O2 plasma will be studied as a replacement for Bosch process to avoid FC residue and facilitate the nanoscale silicon etching with profile control and sufficient mask selectivity preferably at room temperature. The focus will be on the development of a fundamental understanding of the special challenges in SF6-O2 plasma etching at the nanoscale including the physics and chemistry involved. The aim is to establish a generic knowledge platform for future applications such as injection molding.
For this, modern lithography tools (MLA, DUV stepper, e-beam) will be utilized to define the structure down to 10nm critical dimension on top of a silicon wafer. Subsequently, the pattern will be transferred into the silicon layer using a modern plasma tool (SPTS, DRIE-Pegasus). During the process, various etching parameters (flow, pressure, power, etc.) are varied to discover performance-affecting factors. Finally, etching results are characterized under scanning electron microscopy (Carl Zeiss AG, SEM Supra 60VP).
Publications in peer-reviewed journal papers
The results achieved during the ph.d. project have been published on some peer-reviewed journals, which are listed as below:
Publications as first author
[1] The CORE Sequence: A Nanoscale Fluorocarbon-Free Silicon Plasma Etch Process Based on SF6/O2 Cycles with Excellent 3D Profile Control at Room Temperature
- V.T.H. Nguyen, C. Silvestre, P. Shi, R. Cork, F. Jensen, J. Hubner, Jorg ; K. Ma, P. Leussink, M. de Boer, and H. Jansen
- ECS Journal of Solid State Science and Technology 9, p.024002 (2020). DOI
Publications as co-author
[1] Deep reactive ion etching of ‘grass-free’ widely-spaced periodic 2D arrays, using sacrificial structures
- C. M. Silvestre, V. T. H. Nguyen, H. Jansen, and O. Hansen
- Microelectronic Engineering 223, 111228 (2020) DOI