Specific Process Knowledge/Etch/ICP Metal Etcher/silicon oxide - Revision history

Mmat at 14:35, 16 June 2025

2025-06-16T14:35:11Z

← Older revision		Revision as of 16:35, 16 June 2025
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			{{CC-bghe1}}

	'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/ICP_Metal_Etcher/silicon_oxide click here]'''		'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/ICP_Metal_Etcher/silicon_oxide click here]'''
	<br> ~~{{CC-bghe1}}~~		<br>

	=SiO2 etching in the ICP metal=		=SiO2 etching in the ICP metal=

Bghe: /* SiO2 etch using DUV mask */

2023-08-10T11:22:31Z

SiO2 etch using DUV mask

← Older revision		Revision as of 13:22, 10 August 2023
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	*Sample: s007592 ''by bghe@nanolab (2015-06-02)''		*Sample: s007592 ''by bghe@nanolab (2015-06-02)''
	*See Martin Lind Ommen's results with hard masks: [https://labadviser.nanolab.dtu.dk//index.php?title=Specific_Process_Knowledge/Etch/Etching_of_Silicon_Oxide#~~Dry etch with Hard mask~~] <br> There were problems with polymer on the surface after etching.		*See Martin Lind Ommen's results with hard masks: [https://labadviser.nanolab.dtu.dk//index.php?title=Specific_Process_Knowledge/Etch/Etching_of_Silicon_Oxide#Dry_etch_with_Hard_mask] <br> There were problems with polymer on the surface after etching.
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Bghe: /* SiO2 etch using DUV mask */

2023-08-10T11:21:52Z

SiO2 etch using DUV mask

← Older revision		Revision as of 13:21, 10 August 2023
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	*Sample: s007592 ''by bghe@nanolab (2015-06-02)''		*Sample: s007592 ''by bghe@nanolab (2015-06-02)''
	*See Martin Lind Ommen's results with hard masks: [https://labadviser.nanolab.dtu.dk//index.php?title=Specific_Process_Knowledge/Etch/Etching_of_Silicon_Oxide] <br> There were problems with polymer on the surface after etching.		*See Martin Lind Ommen's results with hard masks: [https://labadviser.nanolab.dtu.dk//index.php?title=Specific_Process_Knowledge/Etch/Etching_of_Silicon_Oxide#Dry etch with Hard mask] <br> There were problems with polymer on the surface after etching.
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Bghe: /* SiO2 etch using DUV mask */

2023-08-10T11:21:20Z

SiO2 etch using DUV mask

← Older revision		Revision as of 13:21, 10 August 2023
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	*Sample: s007592 ''by bghe@nanolab (2015-06-02)''		*Sample: s007592 ''by bghe@nanolab (2015-06-02)''
	*See Martin Lind Ommen's results with hard masks ~~in Process2share~~: [~~http~~://~~process2share~~.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/~~Etching_of_SiO2~~] <br> There were problems with polymer on the surface after etching.		*See Martin Lind Ommen's results with hard masks: [https://labadviser.nanolab.dtu.dk//index.php?title=Specific_Process_Knowledge/Etch/Etching_of_Silicon_Oxide] <br> There were problems with polymer on the surface after etching.
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Bghe at 15:06, 6 February 2023

2023-02-06T15:06:45Z

← Older revision		Revision as of 17:06, 6 February 2023
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	'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/ICP_Metal_Etcher/silicon_oxide click here]'''		'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/ICP_Metal_Etcher/silicon_oxide click here]'''
	{{CC-bghe1}}		<br> {{CC-bghe1}}

	=SiO2 etching in the ICP metal=		=SiO2 etching in the ICP metal=

Bghe at 15:06, 6 February 2023

2023-02-06T15:06:34Z

← Older revision		Revision as of 17:06, 6 February 2023
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	'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/ICP_Metal_Etcher/silicon_oxide click here]'''		'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/ICP_Metal_Etcher/silicon_oxide click here]'''
			{{CC-bghe1}}

	=SiO2 etching in the ICP metal=		=SiO2 etching in the ICP metal=
	It is possible to etch SiO2 in the ICP metal etcher but it is not designed for it and we prefer that you do it elsewhere. It is a challenge to get a good selectivity to resist (typically in the range of 1:1 or worse) and it is probably not possible to get a profile angle of 90 degrees. More likely about 75-85 degrees. Different chemistries can be applied either based on CF4 or C4F8. If seems that C4F8 can give the best selectivity to resist (best case I have seem was 1:11 but it depends a lot on the process parameters)). If low coil power is needed CF4 chemistry is used because C4F8 needs a higher power to generate a plasma. ''/bghe 2016-04-25 ''		It is possible to etch SiO2 in the ICP metal etcher but it is not designed for it and we prefer that you do it elsewhere. It is a challenge to get a good selectivity to resist (typically in the range of 1:1 or worse) and it is probably not possible to get a profile angle of 90 degrees. More likely about 75-85 degrees. Different chemistries can be applied either based on CF4 or C4F8. If seems that C4F8 can give the best selectivity to resist (best case I have seem was 1:11 but it depends a lot on the process parameters)). If low coil power is needed CF4 chemistry is used because C4F8 needs a higher power to generate a plasma. ''/bghe 2016-04-25 ''

Bghe: /* SiO2 etching in the ICP metal */

2023-02-06T15:05:02Z

SiO2 etching in the ICP metal

← Older revision		Revision as of 17:05, 6 February 2023
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	'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/ICP_Metal_Etcher/silicon_oxide click here]'''		'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/ICP_Metal_Etcher/silicon_oxide click here]'''
	=SiO2 etching in the ICP metal=		=SiO2 etching in the ICP metal=
	It is possible to etch SiO2 in the ICP metal etcher but it is not designed for it and ~~the results are not fantastic~~. It is a challenge to get a good selectivity to resist (typically in the range of 1:1 or worse) and it is probably not possible to get a profile angle of 90 degrees. More likely about 75-85 degrees. Different chemistries can be applied either based on CF4 or C4F8. If seems that C4F8 can give the best selectivity to resist (best case I have seem was 1:11 but it depends a lot on the process parameters)). If low coil power is needed CF4 chemistry is used because C4F8 needs a higher power to generate a plasma. ''/bghe 2016-04-25 ''		It is possible to etch SiO2 in the ICP metal etcher but it is not designed for it and we prefer that you do it elsewhere. It is a challenge to get a good selectivity to resist (typically in the range of 1:1 or worse) and it is probably not possible to get a profile angle of 90 degrees. More likely about 75-85 degrees. Different chemistries can be applied either based on CF4 or C4F8. If seems that C4F8 can give the best selectivity to resist (best case I have seem was 1:11 but it depends a lot on the process parameters)). If low coil power is needed CF4 chemistry is used because C4F8 needs a higher power to generate a plasma. ''/bghe 2016-04-25 ''

	==Slow etch of SiO2 with resist as masking material - using a 6" carrier wafer with recess ==		==Slow etch of SiO2 with resist as masking material - using a 6" carrier wafer with recess ==

Bghe at 11:31, 6 September 2022

2022-09-06T11:31:20Z

← Older revision		Revision as of 13:31, 6 September 2022
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	'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/ICP_Metal_Etcher/silicon_oxide click here]'''		'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/ICP_Metal_Etcher/silicon_oxide click here]'''
			=SiO2 etching in the ICP metal=
	It is possible to etch SiO2 in the ICP metal etcher but it is not designed for it and the results are not fantastic. It is a challenge to get a good selectivity to resist (typically in the range of 1:1 or worse) and it is probably not possible to get a profile angle of 90 degrees. More likely about 75-85 degrees. Different chemistries can be applied either based on CF4 or C4F8. If seems that C4F8 can give the best selectivity to resist (best case I have seem was 1:11 but it depends a lot on the process parameters)). If low coil power is needed CF4 chemistry is used because C4F8 needs a higher power to generate a plasma. ''/bghe 2016-04-25 ''		It is possible to etch SiO2 in the ICP metal etcher but it is not designed for it and the results are not fantastic. It is a challenge to get a good selectivity to resist (typically in the range of 1:1 or worse) and it is probably not possible to get a profile angle of 90 degrees. More likely about 75-85 degrees. Different chemistries can be applied either based on CF4 or C4F8. If seems that C4F8 can give the best selectivity to resist (best case I have seem was 1:11 but it depends a lot on the process parameters)). If low coil power is needed CF4 chemistry is used because C4F8 needs a higher power to generate a plasma. ''/bghe 2016-04-25 ''

Jmli: /* SiO2 etch with e-beam resist */

2019-11-25T19:37:41Z

SiO2 etch with e-beam resist

← Older revision		Revision as of 21:37, 25 November 2019
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	\|-style="background:Black; color:White"		\|-style="background:Black; color:White"
	!Results		!Results
	!Test on 6" wafer, by Peixiong Shi@~~danchip~~		!Test on 6" wafer, by Peixiong Shi@nanolab
	\|-		\|-
	\|Etch rate of thermal oxide		\|Etch rate of thermal oxide

Jmli: /* SiO2 etch using DUV mask */

2019-11-25T18:20:59Z

SiO2 etch using DUV mask

← Older revision		Revision as of 20:20, 25 November 2019
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	\|Etch rate of thermal oxide		\|Etch rate of thermal oxide
	\|		\|
	*'''145-172 nm/min''' ''by bghe@~~danchip~~ (2015-06-02)''		*'''145-172 nm/min''' ''by bghe@nanolab (2015-06-02)''
	*'''145 nm/min ''' ''by Martin Lind Ommen (fall 2016)''		*'''145 nm/min ''' ''by Martin Lind Ommen (fall 2016)''
	\|-		\|-
	\|Selectivity to resist [:1]		\|Selectivity to resist [:1]
	\| 4-5:1 (SiO2:resist) ''by bghe@~~danchip~~ (2015-06-02)''		\| 4-5:1 (SiO2:resist) ''by bghe@nanolab (2015-06-02)''
	\|-		\|-
	\|Cr etch rate		\|Cr etch rate
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	\|-		\|-
	\|Profile [<sup>o</sup>]		\|Profile [<sup>o</sup>]
	\|86-87 dg ''by bghe@~~danchip~~ (2015-06-02)''		\|86-87 dg ''by bghe@nanolab (2015-06-02)''
	\|-		\|-
	\|Wafer uniformity map (click on the image to view a larger image)		\|Wafer uniformity map (click on the image to view a larger image)