Specific Process Knowledge/Etch/ICP Metal Etcher/Chromium - Revision history

Bghe: /* Chromium etch in ICP metal - small substrate using carrier */

2025-02-18T10:39:24Z

Chromium etch in ICP metal - small substrate using carrier

← Older revision		Revision as of 12:39, 18 February 2025
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	2" Si wafer with Cr laying in a 6" Si wafer with a 4" recess. The area outside the recess was covered by AZ resist.		2" Si wafer with Cr laying in a 6" Si wafer with a 4" recess. The area outside the recess was covered by AZ resist.
	The work was carried out by Erol Zekovic @Nanotech and BGHE@nanolab		The work was carried out by Erol Zekovic @Nanotech and BGHE@nanolab
			* [[/End point\|Cr etch - when to stop using end point detecting]]

	{\| border="2" cellpadding="2" cellspacing="1" style="text-align:center;"		{\| border="2" cellpadding="2" cellspacing="1" style="text-align:center;"
	\|+ '''Cr etch'''		\|+ '''Cr etch'''

Bghe at 11:26, 6 February 2025

2025-02-06T11:26:32Z

← Older revision		Revision as of 13:26, 6 February 2025
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	\|}		\|}

	<gallery caption="Etching lines in 100nm Cr with the Cr etch for 3:30 min with 500 nm DUV resist on a 22mmx22mm piece ''BGHE@Nanolab ~~Feb 2022~~''" perrow="5" widths="400px" heights="300px">		<gallery caption="Etching lines in 100nm Cr with the Cr etch for 3:30 min with 500 nm DUV resist on a 22mmx22mm piece ''BGHE@Nanolab Jan 2023''" perrow="5" widths="400px" heights="300px">
	File:s040321_02.jpg		File:s040321_02.jpg
	File:s040321_05.jpg		File:s040321_05.jpg

Bghe: /* Chromium etch in ICP metal - small substrate using carrier */

2025-02-06T11:23:42Z

Chromium etch in ICP metal - small substrate using carrier

@@ Line 42: / Line 42: @@
 | Was masked by capton tape
 |}
 <gallery caption="Etching lines in 100nm Cr with the Cr etch for 3 min with 300 nm DUV resist ''BGHE@Nanolab Feb 2022''" perrow="5" widths="400px" heights="300px">

Bghe: /* Chromium etch in ICP metal - small substrate using carrier */

2023-07-26T11:22:42Z

Chromium etch in ICP metal - small substrate using carrier

← Older revision		Revision as of 13:22, 26 July 2023
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	The Chromium etch was carried out on the following substrate stack:		The Chromium etch was carried out on the following substrate stack:
	2" Si wafer with Cr laying in a 6" Si wafer with a 4" recess. The area outside the recess was covered by AZ resist.		2" Si wafer with Cr laying in a 6" Si wafer with a 4" recess. The area outside the recess was covered by AZ resist.
	The work was carried out be Erol Zekovic @Nanotech and BGHE@nanolab		The work was carried out by Erol Zekovic @Nanotech and BGHE@nanolab
	{\| border="2" cellpadding="2" cellspacing="1" style="text-align:center;"		{\| border="2" cellpadding="2" cellspacing="1" style="text-align:center;"
	\|+ '''Cr etch'''		\|+ '''Cr etch'''

Bghe: /* Chromium etch of hardmask for silicon nitride etching by Anders Simonsen@nbi.ku */

2023-07-26T11:21:05Z

Chromium etch of hardmask for silicon nitride etching by Anders Simonsen@nbi.ku

← Older revision		Revision as of 13:21, 26 July 2023
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	==Chromium etch of hardmask for silicon nitride etching by Anders Simonsen@nbi.ku ==		==Chromium etch of hardmask for silicon nitride etching by Anders Simonsen@nbi.ku ==
	'''This work was done by Anders Simonsen, KU''' and ''Added by bghe@Nanolab'' <br>		'''This work was done by Anders Simonsen, KU''' and ''Added by bghe@Nanolab'' <br>
	Anders has done some work on optimizing the Cr etch for at ~~20-40~~ nm thick Cr that was to be used as masking for a silicon nitride etch. The Cr etch was carriered out on the ICP metal and the silicon nitride etch was done on the AOE. You can see his results in this summery that he has made:		Anders has done some work on optimizing the Cr etch for at 30 nm thick Cr that was to be used as masking for a 200nm silicon nitride etch. The Cr etch was carriered out on the ICP metal using 180 nm CSAR and the silicon nitride etch was done on the AOE. You can see his results in this summery that he has made:
	* [[Media:report_summer2022 Anders Simonsen bghe edits.pdf \| Cr etch development report summery by Anders Simonesen, summer of 2022 ]]		* [[Media:report_summer2022 Anders Simonsen bghe edits.pdf \| Cr etch development report summery by Anders Simonesen, summer of 2022 ]]
	* [[/Cr etch data from AS \|Here are the raw test data and SEM images from Anders Simonsen]]		* [[/Cr etch data from AS \|Here are the raw test data and SEM images from Anders Simonsen]]

	'''~~Preferer~~ result:'''		'''Prefered result:'''

	The SEM images where done after both the Cr etch and the silicon nitride etch in the AOE using the recipe "SiN_AS". The important thing was to see how well the Cr works for masking the nitride given vertical and smooth sidewalls in the nitride. The thickness of the Cr was 40 nm		The SEM images where done after both the Cr etch and the silicon nitride etch in the AOE using the recipe "SiN_AS". The important thing was to see how well the Cr works for masking the nitride given vertical and smooth sidewalls in the nitride. The thickness of the Cr was 40 nm

Bghe: /* Chromium etch of hardmask for silicon nitride etching by Anders Simonsen@nbi.ku */

2023-07-26T11:18:49Z

Chromium etch of hardmask for silicon nitride etching by Anders Simonsen@nbi.ku

← Older revision		Revision as of 13:18, 26 July 2023
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	'''Preferer result:'''		'''Preferer result:'''

	The SEM images where done after both the Cr etch and the silicon nitride etch in the AOE using the recipe "?". The important thing was to see how well the Cr works for masking the nitride given vertical and smooth sidewalls in the nitride. The thickness of the Cr was 40 nm		The SEM images where done after both the Cr etch and the silicon nitride etch in the AOE using the recipe "SiN_AS". The important thing was to see how well the Cr works for masking the nitride given vertical and smooth sidewalls in the nitride. The thickness of the Cr was 40 nm

	{\| class="wikitable"		{\| class="wikitable"

Bghe: /* Chromium etch of hardmask for silicon nitride etching by Anders Simonsen@nbi.ku */

2023-02-06T14:59:15Z

Chromium etch of hardmask for silicon nitride etching by Anders Simonsen@nbi.ku

← Older revision		Revision as of 16:59, 6 February 2023
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	==Chromium etch of hardmask for silicon nitride etching by Anders Simonsen@nbi.ku ==		==Chromium etch of hardmask for silicon nitride etching by Anders Simonsen@nbi.ku ==
	''Added by bghe@Nanolab'' <br>		'''This work was done by Anders Simonsen, KU''' and ''Added by bghe@Nanolab'' <br>
	Anders has done some work on optimizing the Cr etch for at 20-40 nm thick Cr that was to be used as masking for a silicon nitride etch. The Cr etch was carriered out on the ICP metal and the silicon nitride etch was done on the AOE. You can see his results in this summery that he has made:		Anders has done some work on optimizing the Cr etch for at 20-40 nm thick Cr that was to be used as masking for a silicon nitride etch. The Cr etch was carriered out on the ICP metal and the silicon nitride etch was done on the AOE. You can see his results in this summery that he has made:
	* [[Media:report_summer2022 Anders Simonsen bghe edits.pdf \| Cr etch development report summery by Anders Simonesen, summer of 2022 ]]		* [[Media:report_summer2022 Anders Simonsen bghe edits.pdf \| Cr etch development report summery by Anders Simonesen, summer of 2022 ]]

Bghe at 14:58, 6 February 2023

2023-02-06T14:58:18Z

← Older revision		Revision as of 16:58, 6 February 2023
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	'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/ICP_Metal_Etcher/Chromium click here]'''		'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/ICP_Metal_Etcher/Chromium click here]'''
			<br> {{CC-bghe1}}

	==Chromium etch in ICP metal - small substrate using carrier==		==Chromium etch in ICP metal - small substrate using carrier==

Bghe: /* Chromium etch in ICP metal - small substrate using carrier */

2022-10-05T08:19:10Z

Chromium etch in ICP metal - small substrate using carrier

← Older revision		Revision as of 10:19, 5 October 2022
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	</gallery>		</gallery>

	<gallery caption="Etching lines in 100nm Cr with the Cr etch for 3:20 min with pressure of 30 mTorr with 300 nm DUV resist ''BGHE@Nanolab Oct 2022''" perrow="5" widths="400px" heights="300px">		<gallery caption="Etching lines in 100nm Cr with the Cr etch for 3:20 min with pressure of 30 mTorr and 20C with 300 nm DUV resist ''BGHE@Nanolab Oct 2022''" perrow="5" widths="400px" heights="300px">

	Image:S03385207.jpg		Image:S03385207.jpg

Bghe: /* Chromium etch in ICP metal - small substrate using carrier */

2022-10-05T08:11:51Z

Chromium etch in ICP metal - small substrate using carrier

← Older revision		Revision as of 10:11, 5 October 2022
Line 53:		Line 53:
	</gallery>		</gallery>

			<gallery caption="Etching lines in 100nm Cr with the Cr etch for 3:20 min with pressure of 30 mTorr with 300 nm DUV resist ''BGHE@Nanolab Oct 2022''" perrow="5" widths="400px" heights="300px">

			Image:S03385207.jpg
			Image:S03385211.jpg
			Image:S03385213.jpg
			Image:S03385204.jpg
			Image:S03385215.jpg

			</gallery>