Specific Process Knowledge/Etch/Etching of Silicon/Si etch using ASE - Revision history

Jmli at 08:28, 4 September 2025

2025-09-04T08:28:42Z

← Older revision		Revision as of 10:28, 4 September 2025
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	'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/Etching_of_Silicon/Si_etch_using_ASE click here]'''		'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/Etching_of_Silicon/Si_etch_using_ASE click here]'''
			<!--Checked for updates on 4/9-2025 - ok/jmli -->

	==The Bosch process: Etching of silicon==		==The Bosch process: Etching of silicon==

Jmli: /* Process development */

2023-02-03T07:38:17Z

Process development

← Older revision		Revision as of 09:38, 3 February 2023
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	== Process development ==		== Process development ==
	===Etch of nano sized structures===		===Etch of nano sized structures===
			{{Template:Author-bghe-thissection}}

	*See pxnano2 and comparison with nanotech on the Pegasus: [[Specific Process Knowledge/Etch/DRIE-Pegasus/nanoetch/nano142-pxnano2]]		*See pxnano2 and comparison with nanotech on the Pegasus: [[Specific Process Knowledge/Etch/DRIE-Pegasus/nanoetch/nano142-pxnano2]]

	Older work:		Older work:
	Three different examples of etch are shown here. The masking material was zep520A (80 nm). ~~By BGHE@dtu.dk~~		Three different examples of etch are shown here. The masking material was zep520A (80 nm).

	{\| border="1" cellspacing="1" cellpadding="2" align="left"		{\| border="1" cellspacing="1" cellpadding="2" align="left"

Jmli: /* Etching Si without back side cooling */

2023-02-03T07:37:39Z

Etching Si without back side cooling

← Older revision		Revision as of 09:37, 3 February 2023
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	==Etching Si without back side cooling==		==Etching Si without back side cooling==
			{{Template:Author-bghe-thissection}}

	Etching in an ICP as the ASE without backside cooling normally results in heating up the sample to more than 100 degrees Celsius. This can be problematic especially when using resist as a masking material. <br>		Etching in an ICP as the ASE without backside cooling normally results in heating up the sample to more than 100 degrees Celsius. This can be problematic especially when using resist as a masking material. <br>

Bghe: /* Etch of nano sized structures */

2023-01-27T11:57:38Z

Etch of nano sized structures

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	==Etching Si without back side cooling==		==Etching Si without back side cooling==

Elkh: /* Etch of nano sized structures */

2022-03-15T09:45:48Z

Etch of nano sized structures

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	==Etching Si without back side cooling==		==Etching Si without back side cooling==

Jmli at 14:35, 25 November 2019

2019-11-25T14:35:02Z

← Older revision		Revision as of 16:35, 25 November 2019
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	'''Feedback to this page''': '''[mailto:labadviser@~~danchip~~.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.~~danchip~~.dtu.dk/index.php/Specific_Process_Knowledge/Etch/Etching_of_Silicon/Si_etch_using_ASE click here]'''		'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/Etching_of_Silicon/Si_etch_using_ASE click here]'''


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	*[http://labmanager~~.danchip~~.dtu.dk/d4Show.php?id=1607&mach=105 The QC procedure for ASE]		*[http://labmanager.dtu.dk/d4Show.php?id=1607&mach=105 The QC procedure for ASE]
	*[http://labmanager~~.danchip~~.dtu.dk/view_binary.php?fileId=1751 The newest QC data for ASE]		*[http://labmanager.dtu.dk/view_binary.php?fileId=1751 The newest QC data for ASE]

	{\| {{table}}		{\| {{table}}
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	The recipe Iso is the same recipe as Deepetch but without the passivation steps. <br>		The recipe Iso is the same recipe as Deepetch but without the passivation steps. <br>
	It has been tested once by Filip Sandborg-Olsen @nanotech. <br>		It has been tested once by Filip Sandborg-Olsen @nanotech. <br>
	He etched with 100% load for ~~10min~~. He got an etch rate of 5.51µm/min		He etched with 100% load for 10 min. He got an etch rate of 5.51µm/min

	== Process development ==		== Process development ==
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	Older work:		Older work:
	Three different examples of etch are shown here. The masking material was zep520A (80 nm). By BGHE@~~danchip~~		Three different examples of etch are shown here. The masking material was zep520A (80 nm). By BGHE@dtu.dk

	{\| border="1" cellspacing="1" cellpadding="2" align="left"		{\| border="1" cellspacing="1" cellpadding="2" align="left"

Bghe: /* Etching Si without back side cooling */

2018-03-02T13:37:45Z

Etching Si without back side cooling

← Older revision		Revision as of 15:37, 2 March 2018
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	\|<!--'''Selectivity (resist:Si)'''-->		\|<!--'''Selectivity (resist:Si)'''-->
	1:4.8		1:4.8
	\|<!--'''Etch rate in Si'''-->		\|<!--'''Etch rate in SiO2'''-->
	SRN:1 nm/s		32 nm/min
			SRN:60 nm/min

Bghe: /* Etching Si without back side cooling */

2018-03-02T12:37:00Z

Etching Si without back side cooling

← Older revision		Revision as of 14:37, 2 March 2018
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	This recipe is intended to only for low etch depths that are not very critical with regards to eg. the sidewall profile. For deep etching of silicon you will need to use the bosch process and the coil power.		This recipe is intended to only for low etch depths that are not very critical with regards to eg. the sidewall profile. For deep etching of silicon you will need to use the bosch process and the coil power.

	Recipe name in the ASE: "1si_rie1"		''' Recipe name in the ASE: "1si_rie1" '''
	{\| border="1" cellspacing="1" cellpadding="1" align="left"		{\| border="1" cellspacing="1" cellpadding="1" align="left"
	! Wafer ID		! Wafer ID

Bghe: /* Etching Si without back side cooling */

2018-03-02T12:36:34Z

Etching Si without back side cooling

← Older revision		Revision as of 14:36, 2 March 2018
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	This recipe is intended to only for low etch depths that are not very critical with regards to eg. the sidewall profile. For deep etching of silicon you will need to use the bosch process and the coil power.		This recipe is intended to only for low etch depths that are not very critical with regards to eg. the sidewall profile. For deep etching of silicon you will need to use the bosch process and the coil power.

			Recipe name in the ASE: "1si_rie1"
	{\| border="1" cellspacing="1" cellpadding="1" align="left"		{\| border="1" cellspacing="1" cellpadding="1" align="left"
	! Wafer ID		! Wafer ID

Bghe: /* Etching Si without back side cooling */

2017-11-29T08:54:21Z

Etching Si without back side cooling

← Older revision		Revision as of 10:54, 29 November 2017
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	1:4.8		1:4.8
	\|<!--'''Etch rate in Si'''-->		\|<!--'''Etch rate in Si'''-->
	?		SRN:1 nm/s