Specific Process Knowledge/Etch/DRIE-Pegasus/Pegasus-2/Si Nano etching - Revision history

Jmli at 06:39, 4 April 2025

2025-04-04T06:39:53Z

← Older revision		Revision as of 08:39, 4 April 2025
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	[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/DRIE-Pegasus/Pegasus-2/Nanoscale silicon etching with SF<sub>6</sub> and O<sub>2</sub> click here]'''		[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/DRIE-Pegasus/Pegasus-2/Nanoscale silicon etching with SF<sub>6</sub> and O<sub>2</sub> click here]'''
	<!-- Page reviewed 9/8-2022 jmli -->		<!-- Page reviewed 9/8-2022 jmli -->
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Jmli at 09:37, 9 August 2022

2022-08-09T09:37:23Z

← Older revision		Revision as of 11:37, 9 August 2022
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	'''Feedback to this page:		'''Feedback to this page:
	[mailto:labadviser@~~danchip~~.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.~~danchip~~.dtu.dk/index.php/Specific_Process_Knowledge/Etch/DRIE-Pegasus/Pegasus-2/Nanoscale silicon etching with SF<sub>6</sub> and O<sub>2</sub> click here]'''		[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php/Specific_Process_Knowledge/Etch/DRIE-Pegasus/Pegasus-2/Nanoscale silicon etching with SF<sub>6</sub> and O<sub>2</sub> click here]'''
			<!-- Page reviewed 9/8-2022 jmli -->


	The CORE sequence (meaning Clear, Oxidize, Remove and Etch) is a fluorocarbon-free directional plasma etch procedure that enables a higher selectivity, creates pattern independence of etching profiles and works excellent at room temperature. The CORE process resembles the well-known SF<sub>6</sub>-based Bosch process, but the usual C<sub>4</sub>F<sub>8</sub> inhibitor is replaced by O<sub>2</sub> oxidation with self-limiting characteristics. Therefore the CORE result is similar to Bosch, however has the advantage of preventing the pile-up of fluorocarbon deposits at the topside of deep-etched or nano-sized features. At the same time, process drift is minimized as the reactor wall is staying perfectly clean. The CORE process has shown an excellent performance in high aspect ratio (3D) nanoscale structures with an accurate and controllable etch rate between 1 and 50 nm min<sup>−1</sup> (and SiO<sub>2</sub>-selectivity of ca. 35) using the etch-tool in the RIE-mode. By adding the ICP source (DRIE-mode), a directional etch rate up to 1 μm min<sup>−1</sup> (at 50 sccm SF<sub>6</sub> flow) and selectivity >200 for SiO<sub>2</sub> is possible.		The CORE sequence (meaning Clear, Oxidize, Remove and Etch) is a fluorocarbon-free directional plasma etch procedure that enables a higher selectivity, creates pattern independence of etching profiles and works excellent at room temperature. The CORE process resembles the well-known SF<sub>6</sub>-based Bosch process, but the usual C<sub>4</sub>F<sub>8</sub> inhibitor is replaced by O<sub>2</sub> oxidation with self-limiting characteristics. Therefore the CORE result is similar to Bosch, however has the advantage of preventing the pile-up of fluorocarbon deposits at the topside of deep-etched or nano-sized features. At the same time, process drift is minimized as the reactor wall is staying perfectly clean. The CORE process has shown an excellent performance in high aspect ratio (3D) nanoscale structures with an accurate and controllable etch rate between 1 and 50 nm min<sup>−1</sup> (and SiO<sub>2</sub>-selectivity of ca. 35) using the etch-tool in the RIE-mode. By adding the ICP source (DRIE-mode), a directional etch rate up to 1 μm min<sup>−1</sup> (at 50 sccm SF<sub>6</sub> flow) and selectivity >200 for SiO<sub>2</sub> is possible.

Vthongu at 09:56, 11 May 2020

2020-05-11T09:56:58Z

← Older revision		Revision as of 11:56, 11 May 2020
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	'''Feedback to this page:		'''Feedback to this page:
	[mailto:labadviser@danchip.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.danchip.dtu.dk/index.php/Specific_Process_Knowledge/Etch/DRIE-Pegasus/Pegasus-2/~~Si_Nano_etching~~ click here]'''		[mailto:labadviser@danchip.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.danchip.dtu.dk/index.php/Specific_Process_Knowledge/Etch/DRIE-Pegasus/Pegasus-2/Nanoscale silicon etching with SF<sub>6</sub> and O<sub>2</sub> click here]'''

	The CORE sequence (meaning Clear, Oxidize, Remove and Etch) is a fluorocarbon-free directional plasma etch procedure that enables a higher selectivity, creates pattern independence of etching profiles and works excellent at room temperature. The CORE process resembles the well-known SF<sub>6</sub>-based Bosch process, but the usual C<sub>4</sub>F<sub>8</sub> inhibitor is replaced by O<sub>2</sub> oxidation with self-limiting characteristics. Therefore the CORE result is similar to Bosch, however has the advantage of preventing the pile-up of fluorocarbon deposits at the topside of deep-etched or nano-sized features. At the same time, process drift is minimized as the reactor wall is staying perfectly clean. The CORE process has shown an excellent performance in high aspect ratio (3D) nanoscale structures with an accurate and controllable etch rate between 1 and 50 nm min<sup>−1</sup> (and SiO<sub>2</sub>-selectivity of ca. 35) using the etch-tool in the RIE-mode. By adding the ICP source (DRIE-mode), a directional etch rate up to 1 μm min<sup>−1</sup> (at 50 sccm SF<sub>6</sub> flow) and selectivity >200 for SiO<sub>2</sub> is possible.		The CORE sequence (meaning Clear, Oxidize, Remove and Etch) is a fluorocarbon-free directional plasma etch procedure that enables a higher selectivity, creates pattern independence of etching profiles and works excellent at room temperature. The CORE process resembles the well-known SF<sub>6</sub>-based Bosch process, but the usual C<sub>4</sub>F<sub>8</sub> inhibitor is replaced by O<sub>2</sub> oxidation with self-limiting characteristics. Therefore the CORE result is similar to Bosch, however has the advantage of preventing the pile-up of fluorocarbon deposits at the topside of deep-etched or nano-sized features. At the same time, process drift is minimized as the reactor wall is staying perfectly clean. The CORE process has shown an excellent performance in high aspect ratio (3D) nanoscale structures with an accurate and controllable etch rate between 1 and 50 nm min<sup>−1</sup> (and SiO<sub>2</sub>-selectivity of ca. 35) using the etch-tool in the RIE-mode. By adding the ICP source (DRIE-mode), a directional etch rate up to 1 μm min<sup>−1</sup> (at 50 sccm SF<sub>6</sub> flow) and selectivity >200 for SiO<sub>2</sub> is possible.

Vthongu at 14:44, 10 May 2020

2020-05-10T14:44:12Z

← Older revision		Revision as of 16:44, 10 May 2020
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	The CORE cycle design rules and optimized recipe for the etch rate fixed at 15 nm\min		The CORE cycle design rules and optimized recipe for the etch rate fixed at 15 nm\min


	'''Rule 1''': 2 min E-time needs 2 s O-time. Every 2 min extra E-time will need 1 s extra O-time until a maximum of 14 min E-time.		'''Rule 1''': 2 min E-time needs 2 s O-time. Every 2 min extra E-time will need 1 s extra O-time until a maximum of 14 min E-time.
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	'''Rule 3''': The undercut is roughly half of the gained etch depth per CORE cycle.		'''Rule 3''': The undercut is roughly half of the gained etch depth per CORE cycle.


	Silicon wafers are prepared with 1.5 μm thick resist patterns (AZ MIR 701 DUV resist from MicroChemicals) and exposed using a maskless aligner (MLA150, Heidelberg) to create patterns above 400 nm.		Silicon wafers are prepared with 1.5 μm thick resist patterns (AZ MIR 701 DUV resist from MicroChemicals) and exposed using a maskless aligner (MLA150, Heidelberg) to create patterns above 400 nm.

	For nanosized patterns between 30 and 100 nm, an electron beam writing system (JEOL JBX-9500FSZ) is used with positive tone e-beam resist ZEP520A (ZEON).		For nanosized patterns between 30 and 100 nm, an electron beam writing system (JEOL JBX-9500FSZ) is used with positive tone e-beam resist ZEP520A (ZEON).


	Below are some SEM images of the silicon nanostructures achieved by the CORE process:		Below are some SEM images of the silicon nanostructures achieved by the CORE process:
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	[[File:Fig 13d - 1.png\|800px\|left\|thumb\|'''''Notch-free nanostructures in SOI material derived from the fine-tuned CORE sequence.(Left) Grating with 80 nm periodicity. (Right) RIE lag test structure between 30 and 100 nm.''''']]		[[File:Fig 13d - 1.png\|800px\|left\|thumb\|'''''Notch-free nanostructures in SOI material derived from the fine-tuned CORE sequence.(Left) Grating with 80 nm periodicity. (Right) RIE lag test structure between 30 and 100 nm.''''']]
			<br clear="all" />


	For more details, please contact Henri Jansen (henrija@dtu.dk) or Vy Thi Hoang Nguyen (vthongu@dtu.dk).		For more details, please contact Henri Jansen (henrija@dtu.dk) or Vy Thi Hoang Nguyen (vthongu@dtu.dk).

Vthongu at 14:42, 10 May 2020

2020-05-10T14:42:30Z

← Older revision		Revision as of 16:42, 10 May 2020
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	'''Rule 3''': The undercut is roughly half of the gained etch depth per CORE cycle.		'''Rule 3''': The undercut is roughly half of the gained etch depth per CORE cycle.

			Silicon wafers are prepared with 1.5 μm thick resist patterns (AZ MIR 701 DUV resist from MicroChemicals) and exposed using a maskless aligner (MLA150, Heidelberg) to create patterns above 400 nm.

			For nanosized patterns between 30 and 100 nm, an electron beam writing system (JEOL JBX-9500FSZ) is used with positive tone e-beam resist ZEP520A (ZEON).

	Below are some SEM images of the silicon nanostructures achieved by the CORE process:		Below are some SEM images of the silicon nanostructures achieved by the CORE process:
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	~~Silicon wafers are prepared with 1.5 μm thick resist patterns (AZ MIR 701 DUV resist from MicroChemicals) and exposed using a maskless aligner (MLA150, Heidelberg) to create patterns above 400 nm.~~

	~~For nanosized patterns between 30 and 100 nm, an electron beam writing system (JEOL JBX-9500FSZ) is used with positive tone e-beam resist ZEP520A (ZEON).~~

	For more details, please contact Henri Jansen (henrija@dtu.dk) or Vy Thi Hoang Nguyen (vthongu@dtu.dk).		For more details, please contact Henri Jansen (henrija@dtu.dk) or Vy Thi Hoang Nguyen (vthongu@dtu.dk).

Vthongu at 14:41, 10 May 2020

2020-05-10T14:41:41Z

← Older revision		Revision as of 16:41, 10 May 2020
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	[[File:Fig 13d - 1.png\|800px\|left\|thumb\|'''''Notch-free nanostructures in SOI material derived from the fine-tuned CORE sequence.(Left) Grating with 80 nm periodicity. (Right) RIE lag test structure between 30 and 100 nm.''''']]		[[File:Fig 13d - 1.png\|800px\|left\|thumb\|'''''Notch-free nanostructures in SOI material derived from the fine-tuned CORE sequence.(Left) Grating with 80 nm periodicity. (Right) RIE lag test structure between 30 and 100 nm.''''']]

Vthongu at 14:41, 10 May 2020

2020-05-10T14:41:14Z

← Older revision		Revision as of 16:41, 10 May 2020
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	[[File:Fig 13d - 1.png\|800px\|left\|thumb\|'''''Notch-free nanostructures in SOI material derived from the fine-tuned CORE sequence.(Left) Grating with 80 nm periodicity. (Right) RIE lag test structure between 30 and 100 nm.''''']]		[[File:Fig 13d - 1.png\|800px\|left\|thumb\|'''''Notch-free nanostructures in SOI material derived from the fine-tuned CORE sequence.(Left) Grating with 80 nm periodicity. (Right) RIE lag test structure between 30 and 100 nm.''''']]


	Silicon wafers are prepared with 1.5 μm thick resist patterns (AZ MIR 701 DUV resist from MicroChemicals) and exposed using a maskless aligner (MLA150, Heidelberg) to create patterns above 400 nm.		Silicon wafers are prepared with 1.5 μm thick resist patterns (AZ MIR 701 DUV resist from MicroChemicals) and exposed using a maskless aligner (MLA150, Heidelberg) to create patterns above 400 nm.

	For nanosized patterns between 30 and 100 nm, an electron beam writing system (JEOL JBX-9500FSZ) is used with positive tone e-beam resist ZEP520A (ZEON).		For nanosized patterns between 30 and 100 nm, an electron beam writing system (JEOL JBX-9500FSZ) is used with positive tone e-beam resist ZEP520A (ZEON).

	For more details, please contact Henri Jansen (henrija@dtu.dk) or Vy Thi Hoang Nguyen (vthongu@dtu.dk).		For more details, please contact Henri Jansen (henrija@dtu.dk) or Vy Thi Hoang Nguyen (vthongu@dtu.dk).

Vthongu at 14:40, 10 May 2020

2020-05-10T14:40:55Z

← Older revision		Revision as of 16:40, 10 May 2020
Line 29:		Line 29:

	[[File:Fig 13d - 1.png\|800px\|left\|thumb\|'''''Notch-free nanostructures in SOI material derived from the fine-tuned CORE sequence.(Left) Grating with 80 nm periodicity. (Right) RIE lag test structure between 30 and 100 nm.''''']]		[[File:Fig 13d - 1.png\|800px\|left\|thumb\|'''''Notch-free nanostructures in SOI material derived from the fine-tuned CORE sequence.(Left) Grating with 80 nm periodicity. (Right) RIE lag test structure between 30 and 100 nm.''''']]

			Silicon wafers are prepared with 1.5 μm thick resist patterns (AZ MIR 701 DUV resist from MicroChemicals) and exposed using a maskless aligner (MLA150, Heidelberg) to create patterns above 400 nm.
			For nanosized patterns between 30 and 100 nm, an electron beam writing system (JEOL JBX-9500FSZ) is used with positive tone e-beam resist ZEP520A (ZEON).

			For more details, please contact Henri Jansen (henrija@dtu.dk) or Vy Thi Hoang Nguyen (vthongu@dtu.dk).

Vthongu at 14:34, 10 May 2020

2020-05-10T14:34:10Z

← Older revision		Revision as of 16:34, 10 May 2020
Line 25:		Line 25:


	[[File:Fig 13c.png\|800px\|left\|thumb\|'''''Submicron silicon pillars derived from the fine-tuned CORE sequence.''''' ]		[[File:Fig 13c.png\|800px\|left\|thumb\|'''''Submicron silicon pillars derived from the fine-tuned CORE sequence.''''' ]]


	[[File:Fig 13d - 1.png\|800px\|left\|thumb\|'''''Notch-free nanostructures in SOI material derived from the fine-tuned CORE sequence.(Left) Grating with 80 nm periodicity. (Right) RIE lag test structure between 30 and 100 nm.''''']]		[[File:Fig 13d - 1.png\|800px\|left\|thumb\|'''''Notch-free nanostructures in SOI material derived from the fine-tuned CORE sequence.(Left) Grating with 80 nm periodicity. (Right) RIE lag test structure between 30 and 100 nm.''''']]

Vthongu at 14:33, 10 May 2020

2020-05-10T14:33:46Z

← Older revision		Revision as of 16:33, 10 May 2020
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	[[File:Fig 13a.png\|800px\|~~center~~\|thumb\|'''''Submicron silicon trenches and lines derived from the fine-tuned CORE sequence.''''']]		[[File:Fig 13a.png\|800px\|left\|thumb\|'''''Submicron silicon trenches and lines derived from the fine-tuned CORE sequence.''''']]

	~~'''''Submicron silicon trenches and lines derived from the fine-tuned CORE sequence.'''''~~

			[[File:Fig 13b.png\|800px\|left\|thumb\|'''''Submicron silicon holes derived from the fine-tuned CORE sequence. The side wall angle is ca. 2°.''''' ]]

	~~[[File:Fig 13b.png\|800px]]~~

	'''''Submicron silicon ~~holes~~ derived from the fine-tuned CORE sequence~~. The side wall angle is ca. 2°~~.'''''		[[File:Fig 13c.png\|800px\|left\|thumb\|'''''Submicron silicon pillars derived from the fine-tuned CORE sequence.''''' ]


	~~[[File:Fig 13c.png\|800px]]~~		[[File:Fig 13d - 1.png\|800px\|left\|thumb\|'''''Notch-free nanostructures in SOI material derived from the fine-tuned CORE sequence.(Left) Grating with 80 nm periodicity. (Right) RIE lag test structure between 30 and 100 nm.''''']]

	~~'''''Submicron silicon pillars derived from the fine-tuned CORE sequence.'''''~~

	[[File:Fig 13d - 1.png\|800px]]

	'''''Notch-free nanostructures in SOI material derived from the fine-tuned CORE sequence.(Left) Grating with 80 nm periodicity. (Right) RIE lag test structure between 30 and 100 nm.'''''