LabAdviser/Process Flow/Solar cell process flow - Revision history

Mmat: /* 2 Lithography and oxide etch */

2025-06-17T12:26:13Z

2 Lithography and oxide etch

← Older revision		Revision as of 14:26, 17 June 2025
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	\|Expose photoresist in aligner		\|Expose photoresist in aligner
	\|The resist layer on the wafer frontside is exposed in the aligner, with a dark field mask. Align the mask to wafer flat, and use hard contact.		\|The resist layer on the wafer frontside is exposed in the aligner, with a dark field mask. Align the mask to wafer flat, and use hard contact.
	\|Here you can see a comparison between different [[		\|Here you can see a comparison between different [[Specific Process Knowledge/Lithography/UVExposure\|aligners]].
	Specific Process Knowledge/Lithography/~~Resist#Exposure dose~~\|aligners]].
	\|[[image:2 lithography mask 1.jpg\|250x350px\|center]]		\|[[image:2 lithography mask 1.jpg\|250x350px\|center]]
	\|-		\|-

Mmat at 12:24, 17 June 2025

2025-06-17T12:24:27Z

Mmat at 12:13, 17 June 2025

2025-06-17T12:13:31Z

← Older revision		Revision as of 14:13, 17 June 2025
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	\|4 point probe inspection		\|4 point probe inspection
	\|Measure the metal sheet resistance on the wafer backside with a 4 point probe.		\|Measure the metal sheet resistance on the wafer backside with a 4 point probe.
	\|[[~~Specific_Process_Knowledge~~/Characterization/4-~~Point_Probe~~\|4 point probe]]		\|[[Specific Process Knowledge/Characterization/Four-Point Probe\|4 point probe]]
	\|		\|
	\|-		\|-

Mmat at 21:51, 16 June 2025

2025-06-16T21:51:26Z

← Older revision		Revision as of 23:51, 16 June 2025
Line 25:		Line 25:
	<br clear="all" />A detailed process flow for the solar cell process flow, including all steps and process parameters, can be found here:		<br clear="all" />A detailed process flow for the solar cell process flow, including all steps and process parameters, can be found here:

	Process flow for the solar cell fabrication process as [[~~index.php?title=~~Media:Solar Cell process flow 2024.docx\| Word-]] or [[~~index.php?title=~~Media:Solar Cell process flow 2024.pdf\|PDF-File]].		Process flow for the solar cell fabrication process as [[Media:Solar Cell process flow 2024.docx\| Word-]] or [[Media:Solar Cell process flow 2024.pdf\|PDF-File]].

	==Process flow for a Simple Solar Cell==		==Process flow for a Simple Solar Cell==

Mmat at 10:04, 28 May 2025

2025-05-28T10:04:28Z

← Older revision		Revision as of 12:04, 28 May 2025
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	\|Stylus profiler inspection		\|Stylus profiler inspection
	\|Check the final result by measuring the profile of the aluminium structures on the wafer frontside with a stylus profilometer.		\|Check the final result by measuring the profile of the aluminium structures on the wafer frontside with a stylus profilometer.
	\|[[Specific Process Knowledge/Characterization/~~Profiler~~\|Stylus profilers]]		\|[[Specific Process Knowledge/Characterization/Topographic measurement\|Stylus profilers]]
	\|[[image: Profile_After_lift_off_solar cell.JPG\|250x350px\|center]]		\|[[image: Profile_After_lift_off_solar cell.JPG\|250x350px\|center]]
	\|-		\|-

Mmat: /* 6 SiO2 etch */

2025-05-28T10:03:51Z

6 SiO2 etch

← Older revision		Revision as of 12:03, 28 May 2025
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	\|Stylus profiler inspection		\|Stylus profiler inspection
	\|The step height of the SiO<sub>2</sub> in the doped and undoped areas are measured after the SiO<sub>2</sub> etch.		\|The step height of the SiO<sub>2</sub> in the doped and undoped areas are measured after the SiO<sub>2</sub> etch.
	\|[[Specific Process Knowledge/Characterization/~~Profiler~~\|Stylus profilers]]. The different stylus profilers and their features are described.		\|[[Specific Process Knowledge/Characterization/Topographic measurement\|Stylus profilers]]. The different stylus profilers and their features are described.
	\|		\|
	\|-		\|-

Mmat: /* Process flow */

2025-05-27T15:44:19Z

Process flow

← Older revision		Revision as of 17:44, 27 May 2025
Line 25:		Line 25:
	<br clear="all" />A detailed process flow for the solar cell process flow, including all steps and process parameters, can be found here:		<br clear="all" />A detailed process flow for the solar cell process flow, including all steps and process parameters, can be found here:

	Process flow for the solar cell fabrication process as [[~~media~~:~~Solar_Cell_process_flow_2024~~.docx\| Word-]] or [[~~media~~:~~Solar_Cell_process_flow_2024~~.pdf\|PDF-File]].		Process flow for the solar cell fabrication process as [[index.php?title=Media:Solar Cell process flow 2024.docx\| Word-]] or [[index.php?title=Media:Solar Cell process flow 2024.pdf\|PDF-File]].

	==Process flow==		==Process flow for a Simple Solar Cell==

	Beneath you can see an example of a process recipe with all process steps needed to fabricate a wafer with solar cells. In the process you will find links to the actual machines and processes described in LabAdviser, where you can get more detailed information. Before doing the processing you also have to find the right processing parameters, they are not listed here.		Beneath you can see an example of a process recipe with all process steps needed to fabricate a wafer with solar cells. In the process you will find links to the actual machines and processes described in LabAdviser, where you can get more detailed information. Before doing the processing you also have to find the right processing parameters, they are not listed here.

	''This is a sketchy description of how a solar cell can be fabricated (some details are omitted). ''		''Please note that some of the tools mayb not be up to date in the list below. However, the word and pdf file above have been updated in May 2024.''

			This is a sketchy description of how a solar cell can be fabricated (some details are omitted).
	[[image:Color_explanations.JPG\|130x130px\|center\|]]		[[image:Color_explanations.JPG\|130x130px\|center\|]]

Mmat: Created page with "'''Feedback to this page''': '''[mailto:labadviser@danchip.dtu.dk?Subject=Feed%20back%20from%20page%20http://http://labadviser.danchip.dtu.dk/index.php/Solar_cell_process_flow click here]''' ==Introduction== alt=A wafer with an array of solar cellsA solar cell (photovoltaic cell) converts light energy into electricity. When shining light on to the solar cell, photons will be a..."

2025-05-27T15:42:12Z

Created page with "'''Feedback to this page''': '''[mailto:labadviser@danchip.dtu.dk?Subject=Feed%20back%20from%20page%20http://http://labadviser.danchip.dtu.dk/index.php/Solar_cell_process_flow click here]''' ==Introduction== 275x275px|left|thumb|Figure 1. A wafer with an array of solar cells.|alt=A wafer with an array of solar cellsA solar cell (photovoltaic cell) converts light energy into electricity. When shining light on to the solar cell, photons will be a..."

New page

'''Feedback to this page''': '''[mailto:labadviser@danchip.dtu.dk?Subject=Feed%20back%20from%20page%20http://http://labadviser.danchip.dtu.dk/index.php/Solar_cell_process_flow click here]'''

==Introduction==

[[image:Solar cell.jpg|275x275px|left|thumb|Figure 1. A wafer with an array of solar cells.|alt=A wafer with an array of solar cells]]A solar cell (photovoltaic cell) converts light energy into electricity. When shining light on to the solar cell, photons will be absorbed by the p-doped silicon (absorber) and electron-hole pairs are generated in the crystal. Simultaneously, electron-hole pairs are generated near the p-n junction which contribute to a current flowing from the p- to the n-doped region. Negatively charged carriers move towards the n-doped region, while positively charged carriers move away from the n-doped region.

In order to use the generated electricity, the cell has to be placed in an electric circuit such that electrons can flow freely and continuously from the n-doped region to the p doped region through a load, e.g. a light bulb. To ease the flow of electrons '''metal contacts''' are made on each side of the cell. When the electrons reach the p-doped region through the backside contact they will recombine with the holes. An '''anti-reflective coating''' can be deposited on the front side of the solar cell to minimize the reflectance of the incoming light on the surface, and thereby harvesting more energy from the light source.

[[image:Solarcell2.jpg|303x303px|thumb|Figure 2. Cross-section of the solar cell.|alt=Cross-section of the solar cell.]]

If we take a look at the cross-section of a simple silicon-based solar cell (figure 1), we see a structure as shown in figure 2. The solar cell consists of an '''absorber''' (p-doped bulk silicon crystal), an '''electron membrane''' (shallow n-doped layer on top of the silicon crystal) and '''metal contacts'''.

==Fabrication of a Solar Cell==

The fabrication of any device in the cleanroom starts with developing a process flow (recipe). The process flow includes all steps of the fabrication process in the right order, including crucial investigation methods to ensure quality control.

As a general rule of processing, all high temperature processes are done as early as possible, followed by low temperature processes and metal deposition. Since '''oxide growth''' and '''doping by diffusion''' are high temperature processes, we start by making the '''n-doped''' '''layer''' and '''anti-reflecting coating layer'''. This is done by growing a silicon oxide film and subsequently defining the areas that must be opened to allow doping with phosphorous. The pattering is done by UV lithography of a photo resist, followed by wet etching of the silicon oxide in opened areas and finally the removal of remaining resist. That leaves areas in the silicon open which can are then doped in a high temperature furnace with phosphorous. In a last high temperature furnace, the anti-reflecting coating is made by growing an oxide of a specific thickness (example process: 130 nm).

To make the metal contacts, we have to define the areas where contact to the n-doped layer on the front side is needed. This is done by opening the silicon oxide layer using another UV lithography step followed by another oxide wet etch. This etch step removes the oxide on the backside as well.

Finally, a last lithography step is carried out to define the shape of the contacts and interconnections on the front side. This is done by using a negative photoresist that allows for a '''metal lift-off process'''. Metal is evaporated on the defined resist pattern on the frontside as well as forming the '''contact anode''' on the backside. The resist is subsequently removed (lifted) in acetone or remover 1165 together with the excess metal only leaving metal at the defined areas and at the backside. This process is called lift-off.

[[image:9 Lift-off.jpg|305x305px|left|thumb|Figure 3. Cross section of the clean room fabricated solar cell.|alt=Cross section of the clean room fabricated solar cell.]]
 A detailed process flow for the solar cell process flow, including all steps and process parameters, can be found here:

Process flow for the solar cell fabrication process as [[media:Solar_Cell_process_flow_2024.docx| Word-]] or [[media:Solar_Cell_process_flow_2024.pdf|PDF-File]].

==Process flow==

Beneath you can see an example of a process recipe with all process steps needed to fabricate a wafer with solar cells. In the process you will find links to the actual machines and processes described in LabAdviser, where you can get more detailed information. Before doing the processing you also have to find the right processing parameters, they are not listed here.

''This is a sketchy description of how a solar cell can be fabricated (some details are omitted). ''
[[image:Color_explanations.JPG|130x130px|center|]]

===1 Thermal oxidation===
{| border="1" cellspacing="1" cellpadding="3" style="text-align: left; width: 925px; height: 220px;"
|-

|-
!colspan="2" border="none" style="background:#6495ED; color:black;" align="center" width="225px"|Step
!width="250px" style="background:#6495ED; color:black"|Description
!width="200px" style="background:#6495ED; color:black"|LabAdviser link
!width="260px" style="background:#6495ED; color:black"|Image showing the step
|-

|-
!1.1
|Si wafer
|Start with a 100 mm Si<100> wafer that is single side polished and p doped with boron. This will be the '''absorber''' in the final solar cell.
|[[Specific_Process_Knowledge/Wafer_Information|Wafer information]], types of avaliable wafers are listed.
|[[image:1 Si wafer.jpg|250x350px|center|]]
|-

|- style="background:#BCD4E6; color:black"
!1.2
|RCA clean
|The wafer has to be RCA cleaned, before entering an oxidation furnace.
|[[Specific_Process_Knowledge/Wafer_cleaning/RCA|RCA cleaning]], the different steps in the cleaning procedure are described.
| 
|-

|-
!1.3
|SiO2 dry oxidation
|Grow a dry thermal oxide layer in the Boron Drive-in furnace (A1). The oxide layer will be patterned later on to define '''n-doped''' areas ("'''electron membrane'''".)
|[[Specific_Process_Knowledge/Thermal_Process/A1_Bor_Drive-in_furnace|Boron Drive-in furnace]], info about performance and process parameter range.
||[[image:1_3_oxide.JPG|250x350px|center|]]
|-
|-
|}
 

===2 Lithography and oxide etch ===
{| border="1" cellspacing="1" cellpadding="3" style="text-align: left; width: 925px; height: 220px;"
|-

|-
!colspan="2" border="none" style="background:#6495ED; color:black;" align="center" width="225px"|Step
!width="250px" style="background:#6495ED; color:black"|Description
!width="200px" style="background:#6495ED; color:black"|LabAdviser link
!width="260px" style="background:#6495ED; color:black"|Image showing the step
|-

|-
!2.1
|HMDS surface treatment
|To ensure the resist sticks to the surface, the wafer is HMDS treated before resist spinning.
|[[Specific_Process_Knowledge/Lithography/Pretreatment#HMDS|HMDS oven]]
| 
|-

|-
|- style="background:#BCD4E6; color:black"
!2.2
|Spin resist on wafer backside
|The backside of the wafer needs to be protected, to prevent the SiO2 from being etched in the first etch step (section 3).
|Information about which [[Specific_Process_Knowledge/Lithography/Coaters| resist spinners]] can be used, and which types of resists are available.
|[[image:1 Resist back.jpg|250x350px|center|]]
|-

|-
!2.3
|Spin resist on wafer frontside
|The frontside of the wafer is covered with a resist layer.
|Information about [[Specific_Process_Knowledge/Lithography/UVLithography#Resist_Overview| resist processing]]. Process flows for [[Specific_Process_Knowledge/Lithography/UVLithography#Resist_Overview|positive]], [[Specific_Process_Knowledge/Lithography/UVLithography#Resist_Overview|negative]] and [[Specific_Process_Knowledge/Lithography/UVLithography#Resist_Overview|reversed]] lithography processes.
|[[image:1 Resist front.jpg|250x350px|center|]]
|-

|-
|- style="background:#BCD4E6; color:black"
!2.4
|Expose photoresist in aligner
|The resist layer on the wafer frontside is exposed in the aligner, with a dark field mask. Align the mask to wafer flat, and use hard contact.
|Here you can see a comparison between different [[Specific_Process_Knowledge/Lithography/UVExposure|aligners]].
|[[image:2 lithography mask 1.jpg|250x350px|center]]
|-

|-
!2.5
|Develop photoresist
|In the development step the '''exposed resist is removed,''' so that a resist pattern is formed on the surface.
|Comparison of different [[Specific Process Knowledge/Lithography/Development|developers]].
|[[image:1 Lithography.jpg|250x350px|center]]
|-

|-
|- style="background:#BCD4E6; color:black"
!2.6
|Optical microscope inspection
|Check the results of the exposure and development with an optical microscope by inspecting that the pattern and alignment marks are clearly visible. Right image: top view of alignment marks. The alignment marks will be used to align the wafer to the mask in next lithography step (section 5).
||The different [[Specific_Process_Knowledge/Characterization/Optical_microscope| optical microscopes]] and their features are listed.
|[[image:mask1_SiO-etch-2.jpg|150x150px|center]]
|-

|-
|}
 

===3 SiO2 etch===

{| border="1" cellspacing="1" cellpadding="3" style="text-align: left; width: 925px; height: 220px;"
|-

|-
!colspan="2" border="none" style="background:#6495ED; color:black;" align="center" width="225px"|Step
!width="250px" style="background:#6495ED; color:black"|Description
!width="200px" style="background:#6495ED; color:black"|LabAdviser link
!width="260px" style="background:#6495ED; color:black"|Image showing the step
|-

|-
|-
!3.1
|SiO2 etch
| Etch through the SiO2 layer, where the resist is not covering the SiO2, using Sioetch. Sioetch is BHF with a surfactant.
|[[Specific_Process_Knowledge/Etch/Wet_Silicon_Oxide_Etch_(BHF)|Wet silicon oxide etch (BHF)]]. Etch rates for BHF and HF etches are listed for oxides deposited with different methods.
|[[image:3_1_oxide_etch.JPG|250x350px|center]]
|-

|-
|- style="background:#BCD4E6; color:black"
!3.2
|Inspection
|Inspect the pattern and alignment marks with an optical microscope to check the result of the SiO2 etch.
|The different [[Specific_Process_Knowledge/Characterization/Optical_microscope|optical microscopes]] and their features are listed.
| 
|-

|-
!3.3
|Strip resist
|The resist is removed with acetone. First 2-3 min in rough followed by 5 min in fine strip bath with ultrasound.
|Strip of resist in [[Specific_Process_Knowledge/Lithography/Strip#Rough_and_Fine_Strip|acetone with ultrasound.]] Rough and fine strip baths.
|[[image:3_3_resist_strip.JPG|250x350px|center]]
|-
|-

|}

 

===4 Phosphorous doping ===
{| border="1" cellspacing="1" cellpadding="3" style="text-align: left; width: 925px; height: 220px;"
|-

|-
!colspan="2" border="none" style="background:#6495ED; color:black;" align="center" width="225px"|Step
!width="250px" style="background:#6495ED; color:black"|Description
!width="200px" style="background:#6495ED; color:black"|LabAdviser link
!width="260px" style="background:#6495ED; color:black"|Image showing the step
|-

|-
|-
!4.1
|RCA cleaning
|The wafer has to be RCA cleaned, before entering a pre-deposition furnace. Skip the HF dip to prevent that some of the oxide is removed.
|[[Specific_Process_Knowledge/Wafer_cleaning/RCA|RCA cleaning]], the different steps in the cleaning procedure are described.
| 
|-

|- style="background:#BCD4E6; color:black"
!4.2
|Phosphorus pre-deposition
|Areas that should be '''n-doped''' have been defined by photolithography and etched, and in this step these areas are '''doped by diffusion''' in the Phosphorus Pre-dep furnace.
|[[Specific_Process_Knowledge/Thermal_Process/A4_Phosphor_Pre-dep_furnace|Phosphorus Pre-dep furnace (POCL)]]. Here information about process temperatures and gasses are found.
|[[image:Step 4.2.jpg|250x350px|center]]
|-

|-
|-
!4.3
|Etch of phosphorus glass
|All phosphorus glass and only some of the dry oxide is removed in this step by a BHF etch in the RCA bench for doped wafers.
|[[Specific_Process_Knowledge/Etch/Wet_Silicon_Oxide_Etch_%28BHF%29|BHF etch]].
| 
|-

|- style="background:#BCD4E6; color:black"
!4.4
|SiO2 dry oxidation
|An '''anti reflective coating''' is made by an oxide growth (of a specific thickness).
|[[Specific_Process_Knowledge/Thermal_Process/A3_Phosphor_Drive-in_furnace|Phosphorous Drive-in furnace]] with information about performance and allowed substrates.
|[[image:4_4_oxidation.JPG|250x350px|center]]
|-

|-
|-

|-
|}

 

===5 Lithography – 1.5µm standard ===
{| border="1" cellspacing="1" cellpadding="3" style="text-align: left; width: 925px; height: 220px;"
|-

|-
!colspan="2" border="none" style="background:#6495ED; color:black;" align="center" width="225px"|Step
!width="250px" style="background:#6495ED; color:black"|Description
!width="200px" style="background:#6495ED; color:black"|LabAdviser link
!width="260px" style="background:#6495ED; color:black"|Image showing the step
|-

|-
!5.1
|HMDS surface treatment
|To ensure the resist sticks to the surface, the wafer is HMDS treated before resist spinning.
|Different methods of [[Specific_Process_Knowledge/Lithography/Pretreatment|pretreatment]] prior resist spinning.
| 
|-

|-
|- style="background:#BCD4E6; color:black"
!5.2
|Spin resist on wafer frontside
|The frontside of the wafer is covered with a resist layer
||Information about which [[Specific_Process_Knowledge/Lithography/Coaters| resist coaters]] can be used and [[Specific_Process_Knowledge/Lithography/UVLithography#Resist_Overview|technical reports]] for the different resist types.
|[[image:5_2_resist_spinning.JPG|250x350px|center]]
|-

|-
!5.3
|Expose photoresist in aligner
|The wafer needs to be aligned to the mask. "Hard contact" is recommended.
|Here you can get information about exposure doses and development times depending on different resist types, thicknesses and equipment used. [[Specific_Process_Knowledge/Lithography/UVExposure_Dose|Lists of exposure doses and development times.]]
|[[image:5 lithography mask 2.jpg|250x350px|center]]
|-

|- style="background:#BCD4E6; color:black"
!5.4
|Develop photoresist
|In the development step the '''exposed resist is removed,''' and a resist pattern is formed on the surface.
|Comparison of different [[Specific Process Knowledge/Lithography/Development|developers]]. More details on development times dependent on equipment, resist, thickness and exposure doses can be seen here:[[Specific_Process_Knowledge/Lithography/UVExposure_Dose|Lists of exposure doses and development times.]]
|[[image:5_4_development.JPG|250x350px|center]]
|-

|-
|-
!5.5
|Optical microscope inspection
|Check the pattern and alignment marks with an optical microscope. The alignment marks should be aligned to the marks from the previous lithography step (section 2). Right image: top view of alignment marks after second lithography step.
||The different [[Specific_Process_Knowledge/Characterization/Optical_microscope|optical microscopes]] and their features are listed.
|[[image:Alignment_marks_2.jpg|150x150px|center]]
|-

|-
|}
 

===6 SiO2 etch===

{| border="1" cellspacing="1" cellpadding="3" style="text-align: left; width: 925px; height: 220px;"
|-

|-
!colspan="2" border="none" style="background:#6495ED; color:black;" align="center" width="225px"|Step
!width="250px" style="background:#6495ED; color:black"|Description
!width="200px" style="background:#6495ED; color:black"|LabAdviser link
!width="260px" style="background:#6495ED; color:black"|Image showing the step
|-

|-
|-
!6.1
|SiO2 etch
|Remove oxide with Sioetch in the areas where the '''metallic contact (cathodes''') will be placed (section 8). Sioetch is BHF with a surfactant.
|[[Specific_Process_Knowledge/Etch/Wet_Silicon_Oxide_Etch_(BHF)|Wet Silicon Oxide Etch (BHF)]]. Etch rates for BHF and HF etches are listed for oxides deposited with different methods.
|[[image:6_1_oxide_etch.JPG|250x350px|center]]
|-

|-
|- style="background:#BCD4E6; color:black"
!6.2
|Optical microscope inspection
|Inspect the pattern and alignment marks with an optical microscopes to check the result of the lithography step. The alignment marks should be clearly visible.
|The different [[Specific_Process_Knowledge/Characterization/Optical_microscope|optical microscopes]] and their features are listed.
| 
|-

|-
!6.3
|Strip resist
|The resist is removed with acetone. First 2-3 min in rough followed by 5 min in fine strip bath with ultrasound.
|Comparison of different methods for [[Specific_Process_Knowledge/Lithography/Strip#Strip_Comparison_Table|removing resist.]]
|[[image:6_3_strip_resist.JPG|250x350px|center]]
|-
|-

|-
|- style="background:#BCD4E6; color:black"
!6.4
|Stylus profiler inspection
|The step height of the SiO2 in the doped and undoped areas are measured after the SiO2 etch.
|[[Specific Process Knowledge/Characterization/Profiler|Stylus profilers]]. The different stylus profilers and their features are described.
| 
|-

|}

 

===7 Lithography - Negative process===

{| border="1" cellspacing="1" cellpadding="3" style="text-align: left; width: 925px; height: 220px;"
|-

|-
!colspan="2" border="none" style="background:#6495ED; color:black;" align="center" width="225px"|Step
!width="250px" style="background:#6495ED; color:black"|Description
!width="200px" style="background:#6495ED; color:black"|LabAdviser link
!width="260px" style="background:#6495ED; color:black"|Image showing the step
|-

|-
!7.1
|HMDS surface treatment
|To ensure the resist sticks to the surface, the wafer is HMDS treated before resist spinning.
|Several resist coaters can do the [[Specific_Process_Knowledge/Lithography/Pretreatment#HMDS|HMDS pretreatment]].
| 
|-

|-
|- style="background:#BCD4E6; color:black"
!7.2
|Spin resist on wafer frontside
|The frontside of the wafer is covered with a resist layer.
|Information about which [[Specific_Process_Knowledge/Lithography/Coaters| resist coaters]] can be used, and which types of resists are available. The negative resist n-LOF 2020 are available in the automatic coater [[Specific_Process_Knowledge/Lithography/Coaters#Spin Coater: Gamma UV| Spin Coater: Gamma UV]] and the manual coaters.
|[[image:7_2_spin_resist.JPG|250x350px|center]]
|-

|-
!7.3
|Expose resist in aligner
|The resist is exposed in an aligner, with a bright field mask. The alignment marks on the wafer need to be aligned to the marks on the mask. "Hard contact" is recommended.
|Details on [[Specific_Process_Knowledge/Pattern_Design#Alignment_marks|alignment marks]] (if you would design a mask).
|[[image:7 lithography mask 3.jpg|250x350px|center]]
|-

|- style="background:#BCD4E6; color:black"
!7.4
|Post exposure bake (PEB)
|For negative resist a PEB is crucial, where the wafer with resist is heated after exposure.
|PEB can be done in the [[Specific_Process_Knowledge/Lithography/Development#Developer_TMAH_UV-lithography|Developer TMAH UV-lithography]], or on one of the [[Specific_Process_Knowledge/Lithography/Baking| hot plates and ovens]].
|[[image:7 4 Reversed bake.jpg|250x350px|center]]
|-

|-
!7.5
|Develop photoresist
|The '''non-exposed resist''' is removed, so that a resist pattern is formed on the surface. The resist has negative sloped side walls due to the nature of a negative resist, which is good for lift-off.
|Information about [[Specific_Process_Knowledge/Lithography/UVLithography#Resist_Overview|n-LOF2020]] and the [[Specific_Process_Knowledge/Lithography/LiftOff|lift-off process]].
|[[image:7 6 develop resist.JPG|250x350px|center]]
|-

|- style="background:#BCD4E6; color:black"
!7.6
|Optical microscope inspection
|Check the pattern and alignment marks with an optical microscope. The alignment marks should be aligned to the marks from the two previous lithography steps (section 2 and 5). Right image: alignment marks after the third lithography step.
||The different [[Specific_Process_Knowledge/Characterization/Optical_microscope|optical microscopes]] and their features are listed.
|[[image:mask3- liftoff.jpg|150x150px|center]]
|-

|-
|}
 

===8 Aluminium pattern===

{| border="1" cellspacing="1" cellpadding="3" style="text-align: left; width: 925px; height: 220px;"
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|-
!colspan="2" border="none" style="background:#6495ED; color:black;" align="center" width="225px"|Step
!width="250px" style="background:#6495ED; color:black"|Description
!width="200px" style="background:#6495ED; color:black"|LabAdviser link
!width="260px" style="background:#6495ED; color:black"|Image showing the step
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|-
!8.1
|Aluminium deposition on wafer frontside
|Deposit metal on the wafer frontside to fabricate contacts ('''contact cathodes'''). || [[Specific_Process_Knowledge/Thin_film_deposition/Temescal|Temescal:]] materials can be deposited in this tool. ||[[image:8_1_metal_on_frontside.JPG|250x350px|center]]
|-

|- style="background:#BCD4E6; color:black"
!8.2
|Aluminium deposition on wafer backside
|Deposit metal for contacts ('''contact anode''') on the wafer backside. || [[Specific_Process_Knowledge/Thin_film_deposition/Deposition_of_Aluminium#Comparison_of_Al_deposition_options|Deposition of Aluminum]] can be done with several machines in the cleanroom. || [[image:8_2_after_metal_before_lift.JPG|250x350px|center]]
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!8.3
|Lift-off
|Remove the resist and the metal deposited on top of the areas covered by resist.
|Information about the [[Specific_Process_Knowledge/Lithography/LiftOff|lift-off process]] can be seen here.
|[[image:8_3_lift_off.JPG|250x350px|center]]
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|- style="background:#BCD4E6; color:black"
!8.4
|Optical microscope inspection
|Check the final result with an optical microscope.
|[[Specific_Process_Knowledge/Characterization/Optical_microscope|Optical microscopes]]
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|-color:black"
!8.5
|Stylus profiler inspection
|Check the final result by measuring the profile of the aluminium structures on the wafer frontside with a stylus profilometer.
|[[Specific Process Knowledge/Characterization/Profiler|Stylus profilers]]
|[[image: Profile_After_lift_off_solar cell.JPG|250x350px|center]]
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|- style="background:#BCD4E6; color:black"
!8.6
|4 point probe inspection
|Measure the metal sheet resistance on the wafer backside with a 4 point probe.
|[[Specific_Process_Knowledge/Characterization/4-Point_Probe|4 point probe]]
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← Older revision		Revision as of 14:24, 17 June 2025
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	\|Expose photoresist in aligner		\|Expose photoresist in aligner
	\|The resist layer on the wafer frontside is exposed in the aligner, with a dark field mask. Align the mask to wafer flat, and use hard contact.		\|The resist layer on the wafer frontside is exposed in the aligner, with a dark field mask. Align the mask to wafer flat, and use hard contact.
	\|Here you can see a comparison between different [[~~Specific_Process_Knowledge~~/Lithography/~~UVExposure~~\|aligners]].		\|Here you can see a comparison between different [[
			Specific Process Knowledge/Lithography/Resist#Exposure dose\|aligners]].
	\|[[image:2 lithography mask 1.jpg\|250x350px\|center]]		\|[[image:2 lithography mask 1.jpg\|250x350px\|center]]
	\|-		\|-
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	\|Expose photoresist in aligner		\|Expose photoresist in aligner
	\|The wafer needs to be aligned to the mask. "Hard contact" is recommended.		\|The wafer needs to be aligned to the mask. "Hard contact" is recommended.
	\|Here you can get information about exposure doses and development times depending on different resist types, thicknesses and equipment used. [[~~Specific_Process_Knowledge~~/Lithography/~~UVExposure_Dose~~\|Lists of exposure doses and development times.]]		\|Here you can get information about exposure doses and development times depending on different resist types, thicknesses and equipment used. [[Specific Process Knowledge/Lithography/Resist#Exposure dose\|Lists of exposure doses and development times.]]
	\|[[image:5 lithography mask 2.jpg\|250x350px\|center]]		\|[[image:5 lithography mask 2.jpg\|250x350px\|center]]
	\|-		\|-
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	\|Develop photoresist		\|Develop photoresist
	\|In the development step the '''exposed resist is removed,''' and a resist pattern is formed on the surface.		\|In the development step the '''exposed resist is removed,''' and a resist pattern is formed on the surface.
	\|Comparison of different [[Specific Process Knowledge/Lithography/Development\|developers]]. More details on development times dependent on equipment, resist, thickness and exposure doses can be seen here:[[~~Specific_Process_Knowledge~~/Lithography/~~UVExposure_Dose~~\|Lists of exposure doses and development times.]]		\|Comparison of different [[Specific Process Knowledge/Lithography/Development\|developers]]. More details on development times dependent on equipment, resist, thickness and exposure doses can be seen here:[[Specific Process Knowledge/Lithography/Resist#Exposure dose\|Lists of exposure doses and development times.]]
	\|[[image:5_4_development.JPG\|250x350px\|center]]		\|[[image:5_4_development.JPG\|250x350px\|center]]
	\|-		\|-