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Specific Process Knowledge/Lithography/Aligners/Aligner: Maskless 03 processing

Taran — Sun, 18 Oct 2026 14:13:35 GMT

Back Side Alignment

← Older revision		Revision as of 15:13, 18 October 2026
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	The alignment marks must be placed within the BSA windows. The Overview camera only shows the top side of the substrate, and cannot be used to locate the BSA marks.		The alignment marks must be placed within the BSA windows. The Overview camera only shows the top side of the substrate, and cannot be used to locate the BSA marks, so it's a good idea to include arrows and/or circles around the alignment marks. Remember that a layer exposed on the backside of a substrate must be mirrored across the y-axis in order to match up with the structures on the frontside. A .gds design can be mirrored during conversion using the STEP function, but a .cif design must be mirrored in the design software.

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Specific Process Knowledge/Lithography/Aligners/Aligner: Maskless 02 processing

Taran — Sun, 18 Oct 2026 14:12:37 GMT

Back Side Alignment

← Older revision		Revision as of 15:12, 18 October 2026
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	The alignment marks must be placed within the BSA windows. The Overview camera only shows the top side of the substrate, and cannot be used to locate the BSA marks.		The alignment marks must be placed within the BSA windows. The Overview camera only shows the top side of the substrate, and cannot be used to locate the BSA marks, so it's a good idea to include arrows and/or circles around the alignment marks. Remember that a layer exposed on the backside of a substrate must be mirrored across the y-axis in order to match up with the structures on the frontside. A .gds design can be mirrored during conversion using the STEP function, but a .cif design must be mirrored in the design software.

	{\| cellpadding="2" style="border: 2px solid darkgray;" align="center"		{\| cellpadding="2" style="border: 2px solid darkgray;" align="center"

Specific Process Knowledge/Thin film deposition/Deposition of Vanadium Nitride/VN Reactive Sputtering in Cluster Lesker PC1

Eves — Tue, 13 Oct 2026 18:05:18 GMT

Additional characterization and complete results

← Older revision		Revision as of 19:05, 13 October 2026
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	==Additional characterization and complete results==		==Additional characterization and complete results==

	A complete GiXRD description, including the original diffraction patterns and detailed peak assignments, together with the full XPS composition analysis, REELS results and supporting figures, is available on the corresponding internal LabIntra page. For further information, access to the complete data set or a discussion of the results, please contact <b>Evgeniy Shkondin, DTU Nanolab</b>.		A complete GiXRD description, including the original diffraction patterns and detailed peak assignments, together with the full XPS composition analysis, REELS results and supporting figures, is available on the corresponding internal <b>LabIntra page</b>. For further information, access to the complete data set or a discussion of the results, please contact <b>Evgeniy Shkondin, DTU Nanolab</b>.

Specific Process Knowledge/Thin film deposition/Deposition of V3Si

Eves — Tue, 13 Oct 2026 18:00:20 GMT

Deposition of Vanadium Silicide

← Older revision		Revision as of 19:00, 13 October 2026
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	* [[Specific Process Knowledge/Thin film deposition/Deposition of Vanadium Silicide/V3Si RF-DC Co-Sputtering in Cluster Lesker PC1\|Deposition of Vanadium Silicide (V<sub>3</sub>Si) using RF-DC co-sputtering in Sputter-System Metal-Oxide (PC1), with the V target in Source 5 and the Si target in Source 1]] - Recommended approach.		* [[Specific Process Knowledge/Thin film deposition/Deposition of Vanadium Silicide/V3Si RF-DC Co-Sputtering in Cluster Lesker PC1\|Deposition of Vanadium Silicide (V<sub>3</sub>Si) using RF-DC co-sputtering in Sputter-System Metal-Oxide (PC1), with the V target in Source 5 and the Si target in Source 1]] - <b>Recommended approach.</b>



	* [[Specific Process Knowledge/Thin film deposition/Deposition of Vanadium Silicide/V3Si RF-DC Co-Sputtering in Cluster Lesker PC3\|Deposition of Vanadium Silicide (V<sub>3</sub>Si) using RF-DC co-sputtering in Sputter-System Metal-Nitride (PC3), with the V target in Source 2 and the Si target in Source 1]] - Early study. Use only as inspiration!		* [[Specific Process Knowledge/Thin film deposition/Deposition of Vanadium Silicide/V3Si RF-DC Co-Sputtering in Cluster Lesker PC3\|Deposition of Vanadium Silicide (V<sub>3</sub>Si) using RF-DC co-sputtering in Sputter-System Metal-Nitride (PC3), with the V target in Source 2 and the Si target in Source 1]] - Early study. Use with care and only as inspiration!

	==Comparison of sputter systems for V<sub>3</sub>Si deposition==		==Comparison of sputter systems for V<sub>3</sub>Si deposition==

Specific Process Knowledge/Thin film deposition/Deposition of Vanadium Silicide/V3Si RF-DC Co-Sputtering in Cluster Lesker PC3

Eves — Tue, 13 Oct 2026 17:57:56 GMT

Exploratory V-Si RF-DC co-sputtering in Cluster Lesker PC3

@@ Line 5: / Line 5: @@
 =Exploratory V-Si RF-DC co-sputtering in Cluster Lesker PC3=
-This page documents an early, non-systematic attempt to deposit vanadium silicide by simultaneous RF sputtering of a 4-inch Si target and DC sputtering of a 3-inch V target in the <i>Cluster Lesker PC3</i> chamber. Two otherwise nominally identical depositions were compared: one without RF substrate bias and one with 30 W RF substrate bias.
+This page documents an <b>early</b>, <b>non-systematic attempt</b> to deposit vanadium silicide by simultaneous RF sputtering of a 4-inch Si target and DC sputtering of a 3-inch V target in the <i>Cluster Lesker PC3</i> chamber. Two otherwise nominally identical depositions were compared: one without RF substrate bias and one with 30 W RF substrate bias.
 The experiment gave a striking result. In the measured 30–80&deg; GiXRD range, the unbiased sample showed only reflections assigned to cubic A15 V<sub>3</sub>Si, whereas the sample deposited with 30 W RF substrate bias showed only reflections assigned to hexagonal C40 VSi<sub>2</sub>. The two samples also had very different surface morphologies and sheet resistances.
@@ Line 177: / Line 179: @@
 ! XRR density
 ! XRR roughness
-! Sheet resistance
 |-
 | No substrate bias
@@ Line 186: / Line 187: @@
 | 4.741 g/cm<sup>3</sup>
 | 7.873 nm
-| 29.34 &Omega;/sq
 |-
 | 30 W RF substrate bias (69 V DC bias)
@@ Line 195: / Line 195: @@
 | Not obtained
 | Not obtained
 |}
@@ Line 298: / Line 296: @@
 The 30 W RF-biased film was too rough for a defensible XRR model. No thickness, density, roughness or resistivity should be quoted from this scan. A cross-sectional measurement is needed.
-=SEM surface morphology=
+=Further characterization and data access=
-[[Category:Thin film deposition]]
+SEM images, electrical properties, sheet resistances, and the complete integrated interpretation are available on the corresponding <b>LabIntra page</b> or upon request. Please contact <b>Evgeniy Shkondin, DTU Nanolab</b>, for further details and results.

File:Eves SEM V3Si PC3 bias comparison 20260916.png

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Specific Process Knowledge/Thin film deposition/Deposition of Vanadium Silicide/V3Si RF-DC Co-Sputtering in Cluster Lesker PC3

Eves — Tue, 13 Oct 2026 17:48:28 GMT

Created page with "This page is written by Evgeniy Shkondin @ DTU Nanolab if nothing else is stated. All images and data on this page belong to DTU Nanolab. The exploratory deposition and characterization described below were performed in 2025. =Exploratory V-Si RF-DC co-sputtering in Cluster Lesker PC3= This page documents an early, non-systematic attempt to deposit vanadium silicide by simultaneous RF sputtering of a 4-inch Si target and DC sputt..."

New page

This page is written by Evgeniy Shkondin @ DTU Nanolab if nothing else is stated. 
All images and data on this page belong to DTU Nanolab. 
The exploratory deposition and characterization described below were performed in 2025. 

=Exploratory V-Si RF-DC co-sputtering in Cluster Lesker PC3=

This page documents an early, non-systematic attempt to deposit vanadium silicide by simultaneous RF sputtering of a 4-inch Si target and DC sputtering of a 3-inch V target in the Cluster Lesker PC3 chamber. Two otherwise nominally identical depositions were compared: one without RF substrate bias and one with 30 W RF substrate bias.

The experiment gave a striking result. In the measured 30–80° GiXRD range, the unbiased sample showed only reflections assigned to cubic A15 V3Si, whereas the sample deposited with 30 W RF substrate bias showed only reflections assigned to hexagonal C40 VSi2. The two samples also had very different surface morphologies and sheet resistances.

This PC3 experiment is separate from the later, systematic V3Si process-development study performed in PC1.

==Substrate and deposition conditions==

* Substrate: 150 mm Si(100) wafer
* Surface preparation: native SiO2 removed by HF immediately before deposition
* Si source: 4-inch Si target, RF sputtering
* V source: 3-inch V target, DC sputtering
* Working pressure: 3 mTorr
* Deposition temperature: 600 °C
* Deposition time: 1200 s
* Substrate-bias comparison: no RF bias versus 30 W RF bias
* Recorded DC substrate-bias voltage at 30 W RF bias: 69 V

{| border="2" cellspacing="2" cellpadding="5" class="wikitable" style="text-align:center;"
|+'''PC3 V-Si co-sputtering conditions'''
|-
! Condition
! Si target
! Si power
! Displayed Si voltage
! V target
! V power
! Displayed V voltage
! Pressure
! RF substrate power
! Substrate DC bias
! Temperature
! Time
|-
| No substrate bias
| 4-inch Si
| 120 W RF
| 100 V
| 3-inch V
| 100 W DC
| 322 V
| 3 mTorr
| 0 W
| Not applied
| 600 °C
| 1200 s
|-
| 30 W RF substrate bias
| 4-inch Si
| 120 W RF
| 110 V
| 3-inch V
| 100 W DC
| 309 V
| 3 mTorr
| 30 W
| 69 V
| 600 °C
| 1200 s
|}

Although the applied target powers were unchanged, the displayed Si and V discharge voltages changed when the substrate RF bias was enabled. This shows that the plasma impedance/coupling was not identical in the two runs. Consequently, the elemental rates measured in separate calibration depositions should be treated as nominal flux estimates rather than exact in-situ co-deposition rates.

=Power calibration and estimated V:Si atomic-arrival ratio=

The individual elemental deposition rates measured at 3 mTorr were:

{| border="2" cellspacing="2" cellpadding="5" class="wikitable" style="text-align:center;"
|+'''Individual elemental-rate calibration'''
|-
! Element
! Target size
! Mode
! Power
! Pressure
! Pure-element thickness rate
! Density used
! Molar mass used
|-
| Si
| 4 inch
| RF
| 120 W
| 3 mTorr
| 0.024 nm/s
| 2.329 g/cm3
| 28.0855 g/mol
|-
| V
| 3 inch
| DC
| 100 W
| 3 mTorr
| 0.0700 nm/s
| 6.11 g/cm3
| 50.9415 g/mol
|}

The thickness-rate ratio was therefore:

<math>
\frac{r_V}{r_{Si}}=\frac{0.0700}{0.024}=2.92
</math>

This number cannot be compared directly with the 3:1 atomic stoichiometry of V3Si. For an elemental rate calibration, the atomic arrival rate is proportional to:

<math>
\Phi_i \propto \frac{\rho_i r_i}{M_i}
</math>

where <math>\rho_i</math> is the elemental density, <math>r_i</math> is the pure-element thickness rate, and <math>M_i</math> is the molar mass. The nominal target-derived atomic-arrival ratio is consequently:

<math>
\frac{\Phi_V}{\Phi_{Si}}=
\frac{\rho_V r_V/M_V}{\rho_{Si}r_{Si}/M_{Si}}
=4.22
</math>

Thus, the flux supplied by the two targets was nominally about 80.8 at.% V and 19.2 at.% Si, corresponding to V4.22Si rather than V3Si. The pure-element thickness-rate ratio required for an atomic V:Si ratio of 3 is approximately:

<math>
\left(\frac{r_V}{r_{Si}}\right)_{V_3Si}
=3\frac{M_V/\rho_V}{M_{Si}/\rho_{Si}}
=2.07
</math>

The calibrated target flux was therefore substantially more V-rich than the ideal V3Si value. The formation of V3Si in the unbiased sample cannot be explained by the target flux alone; Si supplied by the oxide-stripped Si wafer must be considered.

==Simple target/substrate mass balance==

Using the calibrated rates and 1200 s deposition time, and assuming for the moment that all deposited V was retained:

* formation of V3Si requires approximately 11.7 nm of substrate-equivalent Si in addition to the Si supplied by the target;
* the corresponding full-retention V3Si layer thickness is approximately 105 nm using a bulk V3Si density of 5.77 g/cm3;
* the measured no-bias XRR thickness was 94.046 nm, about 89% of this simple mass-balance value.

The agreement is reasonable for separately calibrated rates, compound formation, a simplified XRR model, and a process performed at 600 °C. It supports substrate participation but is not an independent composition measurement.

If all calibrated V instead formed VSi2, the limiting mass balance would require approximately 214 nm of additional substrate-equivalent Si and would produce roughly 244 nm of VSi2 using a density of 4.42 g/cm3. These are not measured values for the biased sample. They illustrate that formation of VSi2 throughout the deposited material would require extensive Si uptake from the wafer, a change in retained V flux, or both.

=Characterization methods=

==X-ray reflectivity (XRR)==

XRR measurements were performed using a Rigaku SmartLab X-ray diffractometer. The Cu X-ray tube was operated at 40 kV and 30 mA. The incident optics included an IPS (incident parallel-slit) adapter with a 5° Soller slit. The slit configuration was IS = 0.05 mm, RS1 = 0.05 mm and RS2 = 0.075 mm. The programmed scan used a step size of 0.01° and a counting time of 2 s per point. The MATLAB analysis reads the actual exported angular coordinates and does not assume a fixed data interval.

==Grazing-incidence X-ray diffraction (GiXRD)==

GiXRD measurements were performed using the Rigaku SmartLab instrument with a Cu sealed X-ray tube operated at 40 kV and 30 mA. The scans covered 30–80° in 2θ, using a 0.5 mm incident slit, a step size of 0.01° and a scan speed of 2°/min. The incident angle was fixed at <math>\omega=2^\circ</math> relative to the sample surface.

The shallow fixed incidence increases the film contribution relative to a conventional symmetric scan. Phase assignment is based on the observed reflection series. Reported lattice parameters are approximate because the scans were not subjected to a full instrumental-zero/refraction refinement and the sealed-tube spectrum can contain unresolved Cu Kα contributions.

==Scanning electron microscopy (SEM)==

Plan-view SEM images were recorded at 5.00 kV with the InLens detector. Images were acquired at 200,000× and 300,000× magnification. The original scale bars and acquisition metadata are retained in the TIFF images.

==Sheet resistance==

Room-temperature sheet resistance was measured for both samples. Resistivity is calculated only for the unbiased sample because only that sample has a defensible XRR thickness.

=Results overview=

{| border="2" cellspacing="2" cellpadding="5" class="wikitable" style="text-align:center;"
|+'''Measured and fitted results'''
|-
! Condition
! Crystalline phase detected by GiXRD
! Lattice parameters from GiXRD
! XRR thickness
! XRR density
! XRR roughness
! Sheet resistance
! Calculated resistivity
|-
| No substrate bias
| V3Si, cubic A15
| <math>a=4.731\pm0.003</math> Å1
| 94.046 nm
| 4.741 g/cm3
| 7.873 nm
| 29.34 Ω/sq
| 276 µΩ·cm
|-
| 30 W RF substrate bias (69 V DC bias)
| VSi2, hexagonal C40
| <math>a=4.574</math> Å, <math>c=6.376</math> Å1
| Not obtained; surface too rough for a defensible fit
| Not obtained
| Not obtained
| 6.64 Ω/sq
| Not calculated because thickness is unknown
|}

1 Values are derived from pseudo-Voigt fits to several assigned GiXRD reflections using Cu Kα1 = 1.540593 Å. They should be regarded as approximate GiXRD lattice parameters, not high-resolution lattice refinements.

=Grazing-incidence X-ray diffraction results=

<gallery caption="" widths="850px" heights="600px" perrow="1">
image:eves_GiXRD_V3Si_PC3_bias_comparison_20260916.png|GiXRD comparison of the two PC3 depositions. The temperature shown in the figure is corrected to 600 °C, even though the original data filenames contain 500C.
</gallery>

==Unbiased film: A15 V3Si==

The unbiased sample contains the characteristic A15 V3Si reflection series. The main fitted peaks are:

{| border="1" cellspacing="1" cellpadding="4" class="wikitable" style="text-align:center;"
|-
! Reflection
! Fitted 2θ
! Approximate apparent coherence length2
|-
| V3Si (200)
| 38.03°
| 13.0 nm
|-
| V3Si (210)
| 42.70°
| 10.8 nm
|-
| V3Si (211)
| 46.99°
| 14.4 nm
|-
| V3Si (320)
| 71.95°
| 16.8 nm
|-
| V3Si (321)
| 75.00°
| 12.5 nm
|}

The mean cubic lattice parameter obtained from the five reflections is <math>a=4.731\pm0.003</math> Å. This is slightly larger than the commonly reported room-temperature bulk value of approximately 4.72 Å, but the difference is too small to interpret confidently without a zero-shift/reference correction and a dedicated high-resolution scan.

==30 W RF-biased film: C40 VSi2==

The biased sample contains the reflection series expected for C40 VSi2. The fitted peaks used for the lattice calculation are:

{| border="1" cellspacing="1" cellpadding="4" class="wikitable" style="text-align:center;"
|-
! Reflection
! Fitted 2θ
! Comment
|-
| VSi2 (110)
| 39.43°
| Isolated peak
|-
| VSi2 (111)
| 41.96°
| Fitted together with (003)
|-
| VSi2 (003)
| 42.50°
| Fitted together with (111)
|-
| VSi2 (112)
| 48.98°
| Several C40 reflections are close in this region
|-
| VSi2 (031)
| 73.12°
| High-angle constraint
|-
| VSi2 (032)
| 78.32°
| High-angle constraint
|}

A simultaneous least-squares solution of the hexagonal d-spacing relation gives <math>a=4.574</math> Å and <math>c=6.376</math> Å, in good agreement with reported C40 VSi2 lattice parameters.

In both samples, “single phase” means that no other crystalline phase was resolved above the detection/background limit within the measured 30–80° range. The scans do not exclude amorphous material, a thin interfacial phase, or a minor crystalline fraction hidden by peak overlap.

2 The coherence lengths are Scherrer estimates based on uncorrected fitted FWHM values. Instrumental broadening, microstrain, texture, peak overlap, and the Cu Kα doublet were not separated. These numbers are therefore approximate coherent-domain sizes and must not be equated directly with SEM surface-feature size.

=X-ray reflectivity results=

<gallery caption="" widths="700px" heights="400px" perrow="1">
image:eves_XRR_V3Si_PC3_bias_comparison_20260916.png|XRR comparison and the exported fit for the unbiased sample. The strong damping/absence of useful fringes from the biased sample prevents a reliable thickness fit.
</gallery>

The unbiased sample could be represented by a simplified single vanadium-silicide layer on Si:

* thickness: 94.046 nm;
* fitted density: 4.741 g/cm3;
* fitted layer roughness: 7.873 nm;
* thickness-derived growth rate: 0.0784 nm/s.

The fitted density is about 82% of the 5.77 g/cm3 bulk value used for V3Si. This can reflect porosity/voids, oxidation, model-density/roughness correlation, lateral non-uniformity, or a more complicated interface than the one-layer model. XRR density alone is not a chemical-composition measurement.

The 30 W RF-biased film was too rough for a defensible XRR model. No thickness, density, roughness or resistivity should be quoted from this scan. A cross-sectional measurement is needed.

=SEM surface morphology=

<gallery caption="" widths="800px" heights="570px" perrow="1">
image:eves_SEM_V3Si_PC3_bias_comparison_20260916.png|Plan-view SEM comparison at 200,000× and 300,000×. Original scale bars and microscope metadata are preserved in each panel.
</gallery>

Both films are rough and polycrystalline, but the morphologies differ strongly:

* the unbiased V3Si film consists mainly of much finer, densely distributed granular/nodular surface features, with occasional brighter agglomerates;
* the 30 W-biased VSi2 film contains substantially larger faceted plate-like grains, many with visible terraces or banded surface contrast;
* the coarser faceted morphology of the biased sample is consistent with its strongly damped XRR response, but plan-view SEM cannot provide an RMS roughness or film thickness.

=Electrical results=

The unbiased V3Si sample had a sheet resistance of 29.34 Ω/sq. Combining this value with the XRR thickness gives:

<math>
\rho=R_s t
=29.34\ \Omega/\square \times 94.046\ \mathrm{nm}
=276\ \mu\Omega\cdot\mathrm{cm}
</math>

The 30 W-biased VSi2 sample had a much lower sheet resistance of 6.64 Ω/sq, but this does not by itself demonstrate a lower material resistivity or a better film. Sheet resistance depends on both resistivity and thickness. The biased layer may be considerably thicker because of reaction with the Si wafer, may contain an electrically parallel interfacial/unreacted layer, or may simply have a different intrinsic resistivity and connectivity. Until its thickness and cross-sectional structure are measured, only the sheet resistance should be reported.

=Interpretation of the bias-induced phase change=

The most likely working interpretation is that the oxide-stripped Si substrate was an active reactant and that RF substrate bias changed the early interface reaction sufficiently to select a different silicide phase.

# The targets supplied a V-rich flux. The estimated target-derived atomic ratio was V:Si = 4.22, which is more V-rich than V3Si. Formation of V3Si in the unbiased sample therefore requires some Si uptake from the wafer, but only a modest amount: approximately 11.7 nm of substrate-equivalent Si in the simple full-retention mass balance.
# Bare crystalline Si provides a very large Si reservoir. Earlier V/Si interface studies report that VSi2 is the first silicide phase to nucleate and grow at a single-crystal Si/V interface. More recent V3Si work likewise shows that limiting the available Si favors the V-rich A15 phase, whereas an unrestricted Si supply favors Si-rich silicides.
# The unbiased run may have formed an early V3Si-rich reaction layer. With the V-rich incoming flux, such a layer could kinetically limit further Si transport from the wafer and preserve the A15 phase during the remainder of the 1200 s deposition.
# The 69 V substrate DC bias introduced energetic ion bombardment. Ion bombardment can increase defect generation, surface mobility, atomic mixing and re-sputtering. In this experiment it may have disrupted or delayed formation of the V3Si-rich barrier, enhanced access to substrate Si, and allowed the thermodynamically/kinetically favored Si-rich VSi2 reaction to continue. This is a plausible mechanism, not a direct measurement.
# The bias also changed the plasma state. The Si display changed from 100 to 110 V and the V discharge voltage from 322 to 309 V at fixed applied target powers. The actual V and Si arrival rates may therefore have shifted relative to the separate elemental calibrations. Voltage alone is insufficient to calculate the change in composition.

The data demonstrate that 30 W RF substrate bias is not a small microstructural adjustment for this process. On HF-stripped Si at 600 °C it changes the detected crystalline product from V3Si to VSi2 and produces a much coarser surface morphology.

=Limitations=

* Only two depositions were compared; there is no bias-power series and no repeatability test.
* The elemental deposition rates were measured separately, not simultaneously during co-sputtering at 600 °C.
* No direct V:Si composition measurement is available.
* GiXRD establishes crystalline phase identity within its detection limits but does not quantify amorphous material or reliable phase fractions.
* The biased sample has no measured thickness; therefore its resistivity and true deposition/reaction rate are unknown.
* Plan-view SEM does not reveal the film/substrate interface or how much Si was consumed.
* The influence of the HF-to-load delay and any regrown interfacial oxide was not isolated.
* Phase-pure A15 diffraction does not by itself prove superconductivity; a temperature-dependent resistance measurement is required.

=References=

* W. Zhang et al., “Thin-film synthesis of superconductor-on-insulator A15 vanadium silicide,” Scientific Reports 11, 2358 (2021), [https://doi.org/10.1038/s41598-021-82046-1 DOI: 10.1038/s41598-021-82046-1]. This work discusses control of Si supply during V3Si formation and provides the V/Si molar-volume calculation used as a cross-check here.
* R. J. Schutz et al., “The formation of vanadium silicides at thin-film interfaces,” Journal of Applied Physics 50, 5773–5781 (1979), [https://doi.org/10.1063/1.326718 DOI: 10.1063/1.326718]. This study reports VSi2 as the first silicide phase to nucleate and grow at single-crystal Si/V interfaces.
* M. Bose et al., “In-situ Investigation of the Phase Formation and Superconductivity in V3Si Thin Films at High Temperatures,” [https://arxiv.org/abs/2412.04159 arXiv:2412.04159]. This work shows that interface/barrier consumption and excessive Si access can drive formation of undesirable Si-rich silicides.
* M. Manzo-Perez et al., “Substrate effects on phase formation and interfacial stability in superconducting vanadium silicide thin films,” Applied Physics Letters 127, 122601 (2025), [https://doi.org/10.1063/5.0291576 DOI: 10.1063/5.0291576].

[[Category:Thin film deposition]]
[[Category:Sputtering]]
[[Category:Vanadium silicide]]
[[Category:Cluster Lesker PC3]]

File:Eves XRR V3Si no RF RT PC1 20260915.png

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Specific Process Knowledge/Thin film deposition/Deposition of Vanadium Silicide/V3Si RF-DC Co-Sputtering in Cluster Lesker PC1

Eves — Tue, 13 Oct 2026 17:45:14 GMT

Created page with "This page was written by Evgeniy Shkondin, DTU Nanolab, unless otherwise stated. All images and photographs on this page belong to DTU Nanolab. The fabrication and characterization described below were conducted in 2026 by Evgeniy Shkondin, DTU Nanolab. =Vanadium Silicide RF-DC Co-Sputtering= This document presents the results of vanadium silicide (V3Si) deposition by RF-DC co-sputtering in the Sputter-System..."

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This page was written by Evgeniy Shkondin, DTU Nanolab, unless otherwise stated. 
All images and photographs on this page belong to DTU Nanolab. 
The fabrication and characterization described below were conducted in 2026 by Evgeniy Shkondin, DTU Nanolab. 

=Vanadium Silicide RF-DC Co-Sputtering=

This document presents the results of vanadium silicide (V3Si) deposition by RF-DC co-sputtering in the Sputter-System Metal-Oxide (PC1), commonly referred to as the “Cluster Lesker.” A 3-inch V target was mounted in Source #5 (DC/p-DC), and a 3-inch Si target was mounted in Source #1 (RF).

Vanadium forms several silicide compounds. V3Si is especially interesting because it has the cubic A15 structure and is a metallic, multiband superconductor with a bulk transition temperature of approximately 16-17 K. Its properties are sensitive to composition, atomic ordering, crystalline quality, strain, defects and oxidation.

The films were characterized by X-ray reflectivity (XRR), grazing-incidence X-ray diffraction (GiXRD), X-ray photoelectron spectroscopy (XPS), valence-band XPS, reflection electron energy-loss spectroscopy (REELS), scanning electron microscopy (SEM) and electrical measurements. This shortened page presents the deposition, complete XRR analysis and a concise GiXRD summary.

Substrates used: 150 mm Si wafers with 300 nm thermal SiO2.

The following PC1 process recipes were used:

* MD Co-sputtering_PC1_Src1_Src5_RF_DC
* MD Co-sputtering_PC1_Src1_Src5_RF_DC and RF bias

* Deposition type: RF-DC co-sputtering (upstream)
* Si source power: 120 W RF
* V source power: 145 W DC
* Pressure: 3 mTorr
* RF substrate bias, when used: 30 W
* Deposition time: 1600 s
* Substrate temperatures: room temperature, 300°C, 400°C and 500°C

 


=Deposition conditions=

==Power calibration and choice of V:Si ratio==

To prepare V3Si by co-sputtering, the deposition rates of pure Si and pure V were first measured separately. The required ratio between the two thickness rates is not 3:1. V3Si contains three V atoms for one Si atom, but the two elements have different densities and molar masses; therefore, pure-element thickness rates must be converted to an estimated atomic arrival-rate ratio.

For an elemental sputter source, the atomic flux is proportional to:

<math>
\Phi_i \propto \frac{\rho_i r_i}{M_i}
</math>

where <math>\rho_i</math> is the density of the element, <math>r_i</math> is the deposited thickness rate, and <math>M_i</math> is the molar mass.

For stoichiometric V3Si, the desired atomic ratio is:

<math>
\frac{\Phi_V}{\Phi_{Si}} = 3
</math>

This gives:

<math>
\frac{r_V}{r_{Si}} =
3 \cdot
\frac{M_V/\rho_V}{M_{Si}/\rho_{Si}}
</math>

Using:

* <math>M_V = 50.94</math> g/mol
* <math>\rho_V = 6.11</math> g/cm3
* <math>M_{Si} = 28.09</math> g/mol
* <math>\rho_{Si} = 2.33</math> g/cm3

the required pure-material thickness-rate ratio becomes approximately:

<math>
\frac{r_V}{r_{Si}} \approx 2.07
</math>

Thus, under the assumptions of bulk elemental density, equal sticking probability and transferable single-target calibrations, the pure V thickness rate should be approximately 2.1 times the pure Si thickness rate. A slightly V-rich starting condition was selected to reduce the risk of Si-rich secondary phases such as VSi2:

<math>
\frac{r_V}{r_{Si}} \approx 2.2 - 2.3
</math>

The measured Si deposition rate at 120 W RF was:

<math>
r_{Si} = 0.029 \ \mathrm{nm/s}
</math>

Therefore, the required V deposition rate is:

<math>
r_V = (2.2 - 2.3) \cdot 0.029
</math>

or approximately:

<math>
r_V = 0.064 - 0.067 \ \mathrm{nm/s}
</math>

The measured V deposition rate at 190 W DC was:

<math>
r_V(190W) = 0.087 \ \mathrm{nm/s}
</math>

Assuming an approximately linear dependence of V deposition rate on DC power in this power range, the required V power is:

<math>
P_V =
190 \cdot \frac{0.064 - 0.067}{0.087}
</math>

which gives:

<math>
P_V \approx 140 - 146 \ \mathrm{W}
</math>

Therefore, the co-sputtering condition selected for this test was:

* Si: 120 W RF
* V: 145 W DC

This calibration predicts a slightly V-rich arrival ratio relative to ideal V3Si. It is an initial process estimate, not a direct composition measurement: sputtered-film density, angular distribution, sticking, re-sputtering and source interaction can all make the actual film composition differ from this calculation. The estimated pure-material V rate at 145 W is:

<math>
r_V(145W) = 0.087 \cdot \frac{145}{190} = 0.066 \ \mathrm{nm/s}
</math>

The corresponding pure-material thickness-rate ratio is:

<math>
\frac{r_V}{r_{Si}} =
\frac{0.066}{0.029}
\approx 2.3
</math>

This is close to the intended slightly V-rich process window. XRD and composition measurements are still required to determine whether the deposited film is V3Si-dominant and whether the near-surface composition is representative of the film bulk.

{| border="2" cellspacing="2" cellpadding="2" colspan="10"
|bgcolor="#5CACEE" |'''V3Si RF-DC co-sputtering deposition conditions'''
|-
|

{|{{table}}
| align="center"|

{| border="2" cellspacing="2" cellpadding="5" align="center"

|-
!colspan="10" border="none" style="background:silver; color:black;" align="center"| Deposition conditions using RF-DC co-sputtering

|-
|style="background:WhiteSmoke; color:black"|Wafer number
|style="background:WhiteSmoke; color:black"|Si Power (W)
|style="background:WhiteSmoke; color:black"|Si DC bias (V)
|style="background:WhiteSmoke; color:black"|V Power (W)
|style="background:WhiteSmoke; color:black"|V DC bias (V)
|style="background:WhiteSmoke; color:black"|Pressure (mTorr)
|style="background:WhiteSmoke; color:black"|RF Substrate Power
|style="background:WhiteSmoke; color:black"|RF Substrate DC bias (V)
|style="background:WhiteSmoke; color:black"|Temperature (°C)
|style="background:WhiteSmoke; color:black"|Time (s)

|-
|wafer 1
|120
|189
|145
|309
|3
|-
| -
|RT
|1600

|-
|wafer 2
|120
|189
|145
|309
|3
|-
| -
|RT
|1600

|-
|wafer 3
|120
|189
|145
|309
|3
|-
| -
|RT
|1600

|-
|wafer 4
|120
|189
|145
|309
|3
|-
| -
|RT
|1600

|-
|wafer 5
|120
|189
|145
|309
|3
|-
| -
|300
|1600

|-
|wafer 6
|120
|189
|145
|306
|3
|30
|152
|300
|1600

|-
|wafer 7
|120
|189
|145
|309
|3
|-
| -
|400
|1600

|-
|wafer 8
|120
|189
|145
|305
|3
|30
|152
|400
|1600

|-
|wafer 9
|120
|188
|145
|309
|3
|-
| -
|500
|1600

|-
|wafer 10
|120
|189
|145
|305
|3
|30
|150
|500
|1600

|-
|}

|}
|}
 


=Deposition performance=

{| border="2" cellspacing="2" cellpadding="2" colspan="6"
|bgcolor="#5CACEE" |'''V3Si RF-DC co-sputtering performance'''
|-
|

{|{{table}}
| align="center"|

{| border="2" cellspacing="2" cellpadding="5" align="center"

|-
!colspan="6" border="none" style="background:silver; color:black;" align="center"| Deposition conditions using RF-DC co-sputtering mode

|-
|style="background:WhiteSmoke; color:black"|Wafer number
|style="background:WhiteSmoke; color:black"|RF substrate bias (W)
|style="background:WhiteSmoke; color:black"|Deposition Temperature (°C)
|style="background:WhiteSmoke; color:black"|Total fitted XRR thickness (nm)
|style="background:WhiteSmoke; color:black"|Deposition rate (nm/s)
|style="background:WhiteSmoke; color:black"|Main phase (XRD)

|-
|wafer 1
| -
|RT
|123.3
|0.0771
|weak nanocrystalline V3Si

|-
|wafer 2
| -
|RT
|123.3
|0.0771
|weak nanocrystalline V3Si

|-
|wafer 3
| -
|RT
|123.3
|0.0771
|weak nanocrystalline V3Si

|-
|wafer 4
| -
|RT
|123.3
|0.0771
|weak nanocrystalline V3Si

|-
|wafer 5
| -
|300
|118.1
|0.0737
|V3Si

|-
|wafer 6
|30
|300
|96.5
|0.0603
|V3Si

|-
|wafer 7
| -
|400
|115.6
|0.0722
|V3Si

|-
|wafer 8
|30
|400
|100.4
|0.0627
|V3Si

|-
|wafer 9
| -
|500
|116.2
|0.0725
|V3Si

|-
|wafer 10
|30
|500
|106.6
|0.0666
|V3Si

|-
|}

|}
|}
 


=Interpretation of the first V3Si co-sputtering test=

This first test was intended to determine whether V3Si-dominant films could be obtained by RF-DC co-sputtering of Si and V on Si wafers with 300 nm thermal SiO2. The selected powers, 120 W RF for Si and 145 W DC for V, were derived from independent pure-element rate calibrations and correspond to a slightly V-rich estimated arrival ratio. This calculation defines a useful starting condition, but it is not a direct measurement of the film composition.

Ten wafers were deposited at fixed source powers, pressure and deposition time while the substrate temperature and RF substrate bias were varied. The no-bias films deposited at 300-500 °C have similar XRR-derived net deposition rates of approximately 0.072-0.074 nm/s. Applying 30 W RF substrate bias reduced the measured net rate to 0.060-0.067 nm/s. Relative to the corresponding no-bias films, the reduction is approximately 18% at 300 °C, 13% at 400 °C and 8% at 500 °C. Ion-assisted re-sputtering is one possible explanation, but changes in sticking, densification and the fitted XRR layer model may also contribute.

GiXRD identifies V3Si as the dominant crystalline phase in all heated films. The room-temperature sample shows only a weak, broad feature consistent with poorly crystalline or nanocrystalline V3Si. The scans do not provide quantitative phase fractions, and minor crystalline or amorphous contributions cannot be excluded; therefore, the films are described as V3Si-dominant rather than phase-pure.

The final compound thickness is lower than the arithmetic sum of the independently calibrated pure V and Si thicknesses. Compound density accounts for part of this difference, while calibration geometry, sticking and co-sputtering interactions may account for the remainder. The elemental-rate calculation should therefore be used mainly to select the starting V:Si ratio, whereas XRR provides the experimental net film-growth rate.

==X-Ray Reflectivity (XRR) analysis==

XRR measurements were performed using a Rigaku SmartLab X-ray diffractometer. The Cu X-ray tube was operated at 40 kV and 30 mA. The incident optics included an IPS (incident parallel-slit) adapter with a 5° Soller slit. The slit configuration was IS = 0.05 mm, RS1 = 0.05 mm and RS2 = 0.075 mm. Scans were acquired with a step size of 0.01° and a counting time of 2 s per point.

XRR provides information from the critical-angle region and interference fringes. Their positions and damping were modelled to obtain film thickness, scattering-length-density-related effective mass density and interface/surface roughness. Fitting was carried out in SmartLab Studio. The reported model contains an effective semi-infinite Si-based substrate, a fitted interfacial layer where required, the deposited V3Si main layer and a thin low-density surface overlayer attributed to oxidation, adsorbates and/or model compensation. Neither the surface overlayer nor the fitted interface is chemically identified by XRR.

The reported model tables do not explicitly contain the known 300 nm thermal SiO2 layer. Consequently, the V3Si thickness remains the most robust parameter, while density, roughness and especially the fitted interfacial-layer parameters may partly compensate for the simplified substrate model. A future refit should test an explicit Si/SiO2/interface/V3Si/surface-overlayer stack and compare fit quality and parameter stability.

<gallery caption="" widths="400px" heights="350px" perrow="1">
image:eves_XRR_V3Si_no_RF_RT_PC1_20260915.png|Measured and fitted XRR curves for the V3Si deposited at room temperature and without RF substrate bias. The fringe period changes systematically with film thickness.
</gallery>

<gallery caption="" widths="400px" heights="350px" perrow="2">
image:eves_XRR_V3Si_no_RF_PC1_20260915.png|Measured and fitted XRR curves for the V3Si series deposited at 300-500 °C without RF substrate bias. The fringe period changes systematically with film thickness.
image:eves_XRR_V3Si_with_30W_RF_PC1_20260915.png|Measured and fitted XRR curves for the V3Si series deposited at 300-500 °C with 30W RF substrate bias. The fringe period changes systematically with film thickness.
</gallery>

===Extracted values===

The values below are fit results and should be interpreted as model-dependent effective parameters. Thickness is generally the most robust XRR result. Density and roughness may be correlated with each other and with the assumed surface and interface layers, especially for comparatively thick or rough films.

{| border="2" cellspacing="2" cellpadding="3" colspan="10"
|bgcolor="#B1FB17" |'''XRR results for V3Si layers fitted without a separate interface layer'''
|-
|

{| {{table}}
| align="center" |
{| border="2" cellspacing="2" cellpadding="3" align="center" style="width:1500px"

|-
!colspan="1" style="background:silver; color:black;" align="center" |
|colspan="3" style="background:silver; color:black;" align="center" |Fitted surface overlayer
|colspan="3" style="background:silver; color:black;" align="center" |V3Si main layer
|colspan="3" style="background:silver; color:black;" align="center" |Effective Si-based substrate (300 nm thermal oxide not explicit)

|-
!style="background:WhiteSmoke; color:black;" align="center" |Deposition name
|style="background:WhiteSmoke; color:black;" align="center" |Surface-overlayer thickness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |Surface-overlayer density (g/cm3)
|style="background:WhiteSmoke; color:black;" align="center" |Surface-overlayer roughness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |V3Si thickness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |V3Si density (g/cm3)
|style="background:WhiteSmoke; color:black;" align="center" |V3Si roughness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |Substrate thickness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |Substrate density (g/cm3)
|style="background:WhiteSmoke; color:black;" align="center" |Substrate roughness (nm)

|-
|style="background:White;" |wafer 4
|style="background:White;" |2.000
|style="background:White;" |1.49447
|style="background:White;" |0.748
|style="background:White;" |123.344
|style="background:White;" |5.18332
|style="background:White;" |1.798
|style="background:White;" |<math>\infty</math>
|style="background:White;" |2.33600
|style="background:White;" |0.200

|-
|style="background:White;" |wafer 5
|style="background:White;" |2.000
|style="background:White;" |1.79728
|style="background:White;" |1.954
|style="background:White;" |118.135
|style="background:White;" |5.60387
|style="background:White;" |3.263
|style="background:White;" |<math>\infty</math>
|style="background:White;" |2.33600
|style="background:White;" |0.200

|-
|style="background:White;" |wafer 7
|style="background:White;" |1.989
|style="background:White;" |1.78253
|style="background:White;" |2.043
|style="background:White;" |115.627
|style="background:White;" |5.68528
|style="background:White;" |2.082
|style="background:White;" |<math>\infty</math>
|style="background:White;" |2.33600
|style="background:White;" |0.199

|-
|style="background:White;" |wafer 9
|style="background:White;" |2.000
|style="background:White;" |1.80000
|style="background:White;" |2.262
|style="background:White;" |116.206
|style="background:White;" |5.82937
|style="background:White;" |2.261
|style="background:White;" |<math>\infty</math>
|style="background:White;" |2.33600
|style="background:White;" |0.200

|-
|}
|-
|}
|}

{| border="2" cellspacing="2" cellpadding="3" colspan="13"
|bgcolor="#B1FB17" |'''XRR results for V3Si layers fitted with a separate interface layer'''
|-
|

{| {{table}}
| align="center" |
{| border="2" cellspacing="2" cellpadding="3" align="center" style="width:1950px"

|-
!colspan="1" style="background:silver; color:black;" align="center" |
|colspan="3" style="background:silver; color:black;" align="center" |Fitted surface overlayer
|colspan="3" style="background:silver; color:black;" align="center" |V3Si main layer
|colspan="3" style="background:silver; color:black;" align="center" |Fitted interfacial layer
|colspan="3" style="background:silver; color:black;" align="center" |Effective Si-based substrate (300 nm thermal oxide not explicit)

|-
!style="background:WhiteSmoke; color:black;" align="center" |Deposition name
|style="background:WhiteSmoke; color:black;" align="center" |Surface-overlayer thickness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |Surface-overlayer density (g/cm3)
|style="background:WhiteSmoke; color:black;" align="center" |Surface-overlayer roughness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |V3Si thickness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |V3Si density (g/cm3)
|style="background:WhiteSmoke; color:black;" align="center" |V3Si roughness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |Interface thickness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |Interface density (g/cm3)
|style="background:WhiteSmoke; color:black;" align="center" |Interface roughness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |Substrate thickness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |Substrate density (g/cm3)
|style="background:WhiteSmoke; color:black;" align="center" |Substrate roughness (nm)

|-
|style="background:White;" |wafer 6
|style="background:White;" |1.998
|style="background:White;" |0.88036
|style="background:White;" |0.343
|style="background:White;" |89.925
|style="background:White;" |5.57848
|style="background:White;" |1.864
|style="background:White;" |6.598
|style="background:White;" |5.91227
|style="background:White;" |0.021
|style="background:White;" |<math>\infty</math>
|style="background:White;" |2.33600
|style="background:White;" |0.082

|-
|style="background:White;" |wafer 8
|style="background:White;" |2.000
|style="background:White;" |0.49279
|style="background:White;" |0.552
|style="background:White;" |95.877
|style="background:White;" |5.46046
|style="background:White;" |1.967
|style="background:White;" |4.507
|style="background:White;" |4.74593
|style="background:White;" |0.300
|style="background:White;" |<math>\infty</math>
|style="background:White;" |2.33600
|style="background:White;" |0.200

|-
|style="background:White;" |wafer 10
|style="background:White;" |1.365
|style="background:White;" |1.20000
|style="background:White;" |1.090
|style="background:White;" |99.122
|style="background:White;" |5.68587
|style="background:White;" |1.945
|style="background:White;" |7.461
|style="background:White;" |3.39794
|style="background:White;" |1.321
|style="background:White;" |<math>\infty</math>
|style="background:White;" |2.33600
|style="background:White;" |0.200

|-
|}
|-
|}
|}

For the no-bias series, the fitted main-layer density increases from 5.18 g/cm3 at room temperature to 5.60, 5.69 and 5.83 g/cm3 at 300, 400 and 500 °C. This monotonic trend is consistent with thermally assisted densification and improved ordering. Bulk A15 V3Si is expected to have a density of approximately 5.7 g/cm3; values slightly above this should not be interpreted literally because density and roughness are correlated fit parameters and the substrate stack is simplified.

The biased films have fitted main-layer densities of 5.58, 5.46 and 5.69 g/cm3 at 300, 400 and 500 °C. Bias therefore does not produce a systematic density improvement. The main-layer roughness is lower in every matched biased film than in its no-bias counterpart, but only the biased samples required an additional fitted interfacial layer. This combination is compatible with a smoother top surface together with a more complicated depth-dependent density profile; it is not proof of a chemically distinct interface phase.

For the biased samples, total fitted deposited thickness is the sum of the main and interfacial layers: 96.523 nm for wafer 6, 100.384 nm for wafer 8 and 106.583 nm for wafer 10. These totals are used as the experimental net deposited thicknesses in the performance table.

==Grazing-incidence X-ray diffraction (GiXRD)==

GiXRD measurements were performed on the V3Si-coated Si/SiO2 wafers using the Rigaku SmartLab instrument with a Cu sealed X-ray tube operated at 40 kV and 30 mA. The scans covered a 2θ range of 30–80°, using a 0.5 mm incident slit, a step size of 0.01° and a scan speed of 2°/min. The incident angle was fixed at <math>\omega=2^\circ</math> relative to the sample surface.

The shallow fixed incidence increases the relative contribution from the film compared with a conventional symmetric scan, although substrate, amorphous SiO2 and interface contributions may still be present. Peak positions were compared with reference patterns from the Crystallography Open Database (COD). Because the films may be textured, nanocrystalline and multiphase, the assignments identify the most plausible crystalline phase but do not establish phase purity or quantitative phase fractions.

The room-temperature film shows only a weak, broad feature centred near 43° 2θ, consistent with a poorly crystalline or nanocrystalline V3Si contribution near the expected A15 (210) position. The heated films deposited at 300, 400 and 500 °C, both with and without 30 W RF substrate bias, show the reflection series expected for V3Si as the dominant identified crystalline phase. Minor crystalline phases, amorphous material and depth-dependent composition cannot be excluded from these scans.

A simple local fit places the V3Si-like (210) peak at approximately 42.81°, 42.76° and 42.84° for the no-bias wafers 5, 7 and 9, and at approximately 42.35°, 42.47° and 42.60° for the corresponding 30 W biased wafers 6, 8 and 10. The (200) and (211) reflections show a similar displacement toward lower angles in the biased series. This may reflect a change in lattice parameter, composition or strain, but differences in sample mounting or instrumental alignment must also be excluded. A calibrated full-pattern refinement would be required before reporting quantitative lattice parameters, strain or phase fractions.

The temperature series should be compared using consistently background-corrected peak positions, FWHM values and integrated intensities. Peak narrowing and increasing integrated V3Si intensity can indicate improved coherent-domain size or ordering, whereas texture can alter relative peak intensities independently of phase amount. Accordingly, “V3Si-dominant” is preferred to “phase-pure” for the present data.

=Further characterization and data access=

The full GiXRD description and figures, XPS survey and depth-profile results, valence-band XPS, REELS, SEM cross sections, electrical properties, sheet resistances, calculated resistivities and the complete integrated interpretation are available on the corresponding LabIntra page or upon request. Please contact Evgeniy Shkondin, DTU Nanolab, for further details and results.

Specific Process Knowledge/Thin film deposition/Deposition of V3Si

Eves — Tue, 13 Oct 2026 17:33:28 GMT

Deposition of Vanadium Silicide

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			=Vanadium Silicide (V<sub>3</sub>Si)=

			Vanadium silicide, V<sub>3</sub>Si, is a metallic intermetallic compound with the cubic A15 crystal structure. It is one of the classic A15 superconductors and combines a relatively high superconducting transition temperature with high critical current density and a high upper critical magnetic field. These properties depend strongly on the V/Si ratio, A15 chemical ordering, crystalline quality, strain, film thickness, interfaces and oxygen contamination.

			A particularly important property of V<sub>3</sub>Si is its superconductivity. Well-ordered bulk material can exhibit a superconducting transition temperature, <i>T</i><sub>c</sub>, close to 17 K. Thin-film values are often lower and depend on deposition and annealing conditions; values above 13 K have nevertheless been demonstrated in silicon-compatible structures. Achieving a low and narrow transition requires formation of the A15 phase while limiting competing phases such as Si-rich VSi<sub>2</sub>, unreacted V and oxygen-containing compounds.

			V<sub>3</sub>Si is therefore of interest for superconducting and quantum technologies, particularly where compatibility with silicon processing is important. Possible applications include superconducting interconnects, Josephson junctions, superconducting quantum interference devices (SQUIDs), microwave and kinetic-inductance structures, and other cryogenic components for silicon-integrated quantum circuits. Its relatively high <i>T</i><sub>c</sub> and critical field are attractive, but low microwave loss, reproducible interfaces, patterning behaviour and coherence performance must be demonstrated before V<sub>3</sub>Si can be considered a mature quantum-circuit material. It remains less established for quantum devices than Al, Nb, NbN, NbTiN or TiN.

			Outside quantum-device research, V<sub>3</sub>Si is also studied for superconducting radio-frequency components, high-field superconducting structures and fundamental investigations of A15 superconductivity. In every application, a room-temperature metallic resistance or a V<sub>3</sub>Si-like diffraction pattern is not by itself proof of superconductivity. Temperature-dependent electrical measurements through <i>T</i><sub>c</sub>, preferably together with critical-current and magnetic-field measurements, are required.

			==Deposition of Vanadium Silicide==

			At DTU Nanolab, V<sub>3</sub>Si thin films are developed by RF-DC co-sputtering from separate elemental V and Si targets in an Ar atmosphere. Independent control of the two sources makes it possible to tune the V/Si arrival-rate ratio, while substrate temperature and optional RF substrate bias provide additional control over film density, crystallinity and net deposition rate.

			The preferred tool for this application is a cluster-based, multi-chamber, high-vacuum sputtering system, commonly referred to as the "[[Specific Process Knowledge/Thin film deposition/Cluster-based multi-chamber high vacuum sputtering deposition system\|Cluster Lesker]]." The characterized PC1 process is described in detail here:



			* [[Specific Process Knowledge/Thin film deposition/Deposition of Vanadium Silicide/V3Si RF-DC Co-Sputtering in Cluster Lesker PC1\|Deposition of Vanadium Silicide (V<sub>3</sub>Si) using RF-DC co-sputtering in Sputter-System Metal-Oxide (PC1), with the V target in Source 5 and the Si target in Source 1]] - Recommended approach.



			* [[Specific Process Knowledge/Thin film deposition/Deposition of Vanadium Silicide/V3Si RF-DC Co-Sputtering in Cluster Lesker PC3\|Deposition of Vanadium Silicide (V<sub>3</sub>Si) using RF-DC co-sputtering in Sputter-System Metal-Nitride (PC3), with the V target in Source 2 and the Si target in Source 1]] - Early study. Use only as inspiration!

			==Comparison of sputter systems for V<sub>3</sub>Si deposition==

			{\|border="1" cellspacing="1" cellpadding="3" style="text-align:left;"
			\|-

			\|-
			\|-style="background:silver; color:black"
			!
			![[Specific_Process_Knowledge/Thin_film_deposition/Cluster-based_multi-chamber_high_vacuum_sputtering_deposition_system\|Sputter-System Metal-Oxide (PC1)]]
			![[Specific_Process_Knowledge/Thin_film_deposition/Cluster-based_multi-chamber_high_vacuum_sputtering_deposition_system\|Sputter-System Metal-Nitride (PC3)]]
			\|-

			\|-
			\|-style="background:WhiteSmoke; color:black"
			!General description
			\|
			*RF-DC co-sputtering from independent Si and V targets
			*Optional RF substrate bias
			*Characterized V<sub>3</sub>Si process available
			\|
			*RF-DC co-sputtering is technically possible
			*Process parameters require separate qualification
			\|-

			\|-
			\|-style="background:LightGrey; color:black"
			!Stoichiometry
			\|
			*Tunable through the independently calibrated V and Si deposition rates
			\|
			*Tunable through the independently calibrated V and Si deposition rates
			\|-

			\|-
			\|-style="background:WhiteSmoke; color:black"
			!Film thickness
			\|
			*Limited by process time
			*The characterized series produced approximately 100-120 nm in 1600 s; RF bias reduced the net thickness

			\|
			*Limited by process time
			*Deposition rate depends on the selected V and Si powers and must be calibrated for the source configuration
			\|-

			\|-
			\|-style="background:LightGrey; color:black"
			!Process temperature
			\|
			*Up to 600 °C
			\|
			*Up to 600 °C
			\|-

			\|-
			\|-style="background:WhiteSmoke; color:black"
			!Step coverage
			\|
			*Some step coverage possible
			\|
			*Some step coverage possible
			\|-

			\|-
			\|-style="background:LightGrey; color:black"
			!Film quality
			\|
			*Deposition on one side of the substrate
			*Composition, A15 phase formation, density and resistivity depend on power ratio, temperature and substrate bias
			\|
			*Deposition on one side of the substrate
			*Composition and phase formation require process development and characterization
			\|-

			\|-
			\|-style="background:WhiteSmoke; color:black"
			!Batch size
			\|
			*Many smaller samples
			*Up to ten 100 mm or 150 mm wafers
			\|
			*Many smaller samples
			*Up to ten 100 mm or 150 mm wafers
			\|-

			\|-
			\|-style="background:LightGrey; color:black"
			!'''Allowed materials'''
			\|
			*Most vacuum-compatible materials, provided that they do not outgas significantly and are not highly toxic; see the cross-contamination sheets
			\|
			*Most vacuum-compatible materials, provided that they do not outgas significantly and are not highly toxic; see the cross-contamination sheets
			\|-
			\|}

			<br clear="all" />

Specific Process Knowledge/Thin film deposition/Deposition of V3Si

Eves — Tue, 13 Oct 2026 17:22:59 GMT

New page

Specific Process Knowledge/Thin film deposition

Eves — Tue, 13 Oct 2026 17:21:19 GMT

Choose material to deposit

← Older revision		Revision as of 18:21, 13 October 2026
(One intermediate revision by the same user not shown)
Line 85:		Line 85:
	[[/Deposition of NiFe\|NiFe]]<br/>		[[/Deposition of NiFe\|NiFe]]<br/>
	[[/Deposition of NiV\|NiV]] alloy <br/>		[[/Deposition of NiV\|NiV]] alloy <br/>
			[[/Deposition of V3Si\|V<sub>3</sub>Si]] alloy <br/>
	[[/Deposition of TiW\|TiW]] alloy (10%/90% by weight) <br/>		[[/Deposition of TiW\|TiW]] alloy (10%/90% by weight) <br/>
	[[/Deposition of MoSi\|MoSi]] alloy (50%/50% by At.%) <br/>		[[/Deposition of MoSi\|MoSi]] alloy (50%/50% by At.%) <br/>

Specific Process Knowledge/Thin film deposition/Deposition of Vanadium Nitride

Eves — Tue, 13 Oct 2026 17:19:04 GMT

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Specific Process Knowledge/Thin film deposition/Deposition of Vanadium Nitride/VN Reactive Sputtering in Cluster Lesker PC1

Eves — Tue, 13 Oct 2026 17:02:25 GMT

Created page with "This page was written by Evgeniy Shkondin, DTU Nanolab, unless otherwise stated. All images and photographs on this page belong to DTU Nanolab. The fabrication and characterization described below were carried out in 2026 by Evgeniy Shkondin, DTU Nanolab. =Vanadium Nitride p-DC Reactive Sputtering= This document presents the development and characterization of vanadium nitride (VNx) thin films deposited by react..."

New page

This page was written by Evgeniy Shkondin, DTU Nanolab, unless otherwise stated. 
All images and photographs on this page belong to DTU Nanolab. 
The fabrication and characterization described below were carried out in 2026 by Evgeniy Shkondin, DTU Nanolab. 

=Vanadium Nitride p-DC Reactive Sputtering=

This document presents the development and characterization of vanadium nitride (VNx) thin films deposited by reactive pulsed-DC (p-DC) sputtering in the Metal-Oxide sputter system (PC1), commonly referred to as the “Cluster Lesker.” A 3-inch elemental V target was mounted in Source #5, which can be operated in DC or p-DC mode.

Vanadium nitride is a hard, electrically conductive refractory ceramic with good resistance to wear, corrosion and elevated temperatures. Depending on composition and defect concentration, VN can also become superconducting at low temperature. These properties make VNx interesting for protective coatings, diffusion barriers, electrodes and superconducting thin-film devices. Its electrical and structural behaviour is particularly sensitive to the N/V ratio, vacancies, secondary phases, oxygen contamination and deposition temperature.

Two related process series were prepared to separate the effects of reactive-gas fraction and substrate temperature. Wafers 1–5 were deposited at 400 °C, whereas wafers 6–10 were deposited at 600 °C. Within each series, the N2 fraction in a constant total Ar/N2 flow of 40 sccm was increased from 5 to 25%. The pairs 1/6, 2/7, 3/8, 4/9 and 5/10 therefore have the same gas composition but different deposition temperatures.

All fabrication and characterization were carried out in 2026 by Evgeniy Shkondin, DTU Nanolab. Film thickness, density and roughness were investigated by X-ray reflectivity (XRR); crystalline phases were examined by grazing-incidence X-ray diffraction (GiXRD); surface-region composition was measured by X-ray photoelectron spectroscopy (XPS); and the near-elastic loss structure was studied by reflection electron energy-loss spectroscopy (REELS). Sheet resistance was also measured to follow changes in electrical performance.

The substrates were 150 mm Si wafers coated with 300 nm of thermally grown SiO2. The oxide provides electrical isolation and should be considered when interpreting substrate, background and interface-related features.

The baseline recipe used in the Metal-Oxide sputter system (PC1) was as follows:

* Recipe name: MD PC1 Src5 p-DC Downstream with reactive N2 gas

* Deposition type: R p-DC
* Power: 400 W
* Pressure: 3 mTorr
* Gas: Ar and N2 (Variable)
* Frequency: 100 kHz
* Reverse time: 1 µs
* Deposition time: 1800 s
* Temperatures: 400°C and 600°C

All depositions were performed for 1800 s at 400 W and 3 mTorr. The total process-gas flow was kept at 40 sccm; only the Ar/N2 balance and substrate temperature were changed. Pulsed-DC operation was selected to improve discharge stability during reactive sputtering and to reduce the probability of arcing as the V target surface became progressively nitrided.
 


=Deposition conditions=

The table below lists the recorded process parameters for all ten wafers. Wafers 1–5 form the 400 °C series and wafers 6–10 the 600 °C series. In both series, the N2 flow was raised in 2 sccm steps while the Ar flow was reduced by the same amount, maintaining a total flow of 40 sccm. Apart from substrate temperature and gas composition, the nominal settings were kept constant. The reported DC-bias values represent the measured discharge-voltage magnitude during operation.

{| border="2" cellspacing="2" cellpadding="2" colspan="10"
|bgcolor="#5CACEE" |'''VNx Reactive p-DC sputtering deposition conditions'''
|-
|

{|{{table}}
| align="center"|

{| border="2" cellspacing="2" cellpadding="5" align="center"

|-
!colspan="10" border="none" style="background:silver; color:black;" align="center"| Deposition conditions using Reactive p-DC mode

|-
|style="background:WhiteSmoke; color:black"|Wafer number
|style="background:WhiteSmoke; color:black"|Power (W)
|style="background:WhiteSmoke; color:black"|DC bias (V)
|style="background:WhiteSmoke; color:black"|Pressure (mTorr)
|style="background:WhiteSmoke; color:black"|Frequency (kHz)
|style="background:WhiteSmoke; color:black"|Reverse time (µs)
|style="background:WhiteSmoke; color:black"|Temperature (°C)
|style="background:WhiteSmoke; color:black"|Ar flow (sccm)
|style="background:WhiteSmoke; color:black"|N2 flow (sccm)
|style="background:WhiteSmoke; color:black"|Time (s)

|-
|wafer 1
|400
|417
|3
|100
|1
|400
|38
|2
|1800

|-
|wafer 2
|400
|432
|3
|100
|1
|400
|36
|4
|1800

|-
|wafer 3
|400
|440
|3
|100
|1
|400
|34
|6
|1800

|-
|wafer 4
|400
|449
|3
|100
|1
|400
|32
|8
|1800

|-
|wafer 5
|400
|454
|3
|100
|1
|400
|30
|10
|1800

|-
|wafer 6
|400
|417
|3
|100
|1
|600
|38
|2
|1800

|-
|wafer 7
|400
|426
|3
|100
|1
|600
|36
|4
|1800

|-
|wafer 8
|400
|436
|3
|100
|1
|600
|34
|6
|1800

|-
|wafer 9
|400
|446
|3
|100
|1
|600
|32
|8
|1800

|-
|wafer 10
|400
|451
|3
|100
|1
|600
|30
|10
|1800

|-
|}

|}
|}
 

The discharge voltage increases as the N2 fraction is raised: from 417 to 454 V at 400 °C and from 417 to 451 V at 600 °C. Such a systematic change is consistent with a changing target-surface state during reactive sputtering. It is therefore important not to interpret the N2 percentage in the gas as the stoichiometric value x in VNx; the relationship between gas flow and incorporated nitrogen is generally nonlinear.

=Deposition performance=

The performance table combines the measured thickness, calculated average deposition rate, principal GiXRD phase assignment and sheet resistance. The average rate was calculated simply as film thickness divided by the 1800 s deposition time. No reliable thickness was available for wafers 1 and 6, so their deposition rates are left blank.

{| border="2" cellspacing="2" cellpadding="2" colspan="10"
|bgcolor="#5CACEE" |'''VNx Reactive p-DC sputtering deposition performance'''
|-
|

{|{{table}}
| align="center"|

{| border="2" cellspacing="2" cellpadding="5" align="center"

|-
!colspan="10" border="none" style="background:silver; color:black;" align="center"| Deposition performance summary for reactive p-DC sputtering

|-
|style="background:WhiteSmoke; color:black"|Wafer number
|style="background:WhiteSmoke; color:black"|N2 percentage (%)
|style="background:WhiteSmoke; color:black"|Deposition Temperature (°C)
|style="background:WhiteSmoke; color:black"|Measured thickness (nm)
|style="background:WhiteSmoke; color:black"|Deposition rate (nm/s)
|style="background:WhiteSmoke; color:black"|Main phase (XRD)
|style="background:WhiteSmoke; color:black"|Sheet resistance (Ohm/sq)

|-
|wafer 1
|5
|400
| -
| -
|β-V2Si
|4.24

|-
|wafer 2
|10
|400
|250
|0.1388
|mixture of β-V2Si and cubic VN
|7.15

|-
|wafer 3
|15
|400
|200.2
|0.1112
|cubic VN
|6.63

|-
|wafer 4
|20
|400
|167.2
|0.0930
|cubic VN
|5.50

|-
|wafer 5
|25
|400
|149.6
|0.0831
|cubic VN
|4.83

|-
|wafer 6
|5
|600
| -
| -
|β-V2Si
|4.33

|-
|wafer 7
|10
|600
|218
|0.1211
|mixture of β-V2Si and cubic VN
|5.54

|-
|wafer 8
|15
|600
|187.5
|0.1042
|cubic VN
|6.39

|-
|wafer 9
|20
|600
|161
|0.089
|cubic VN
|6.40

|-
|wafer 10
|25
|600
|144.5
|0.080
|cubic VN
|6.31

|-
|}

|}
|}
 

The deposition rate decreases markedly as the reactive-gas fraction increases. At 400 °C it falls from 0.1388 nm/s for wafer 2 to 0.0831 nm/s for wafer 5, while at 600 °C it falls from 0.1211 nm/s for wafer 7 to approximately 0.080 nm/s for wafer 10. This behaviour is typical of a reactive-sputtering process in which formation of a nitride-rich target surface reduces the effective sputter yield. A contribution from composition-dependent resputtering at the growing film cannot be excluded.

The GiXRD assignments show the same general phase sequence at both temperatures: the 5% N2 samples are assigned mainly to β-V2Si, the 10% samples contain both β-V2Si and cubic VN, and the 15–25% samples are dominated by cubic VN. These labels are based on diffraction-pattern matching and should not be interpreted as quantitative phase fractions.

Sheet resistance should be considered together with thickness. For example, a thinner film may have a similar sheet resistance while possessing a different resistivity. Using <math>\rho=R_s t</math>, the approximate resistivity decreases from about 179 to 72 µΩ·cm across wafers 2–5 and from about 121 to 91 µΩ·cm across wafers 7–10. These values are useful for comparison within this sample set, although contact geometry, thickness uncertainty and any parallel conduction paths should be considered.

=Characterization=

The following sections describe the structural, compositional and near-surface characterization. For clarity, each method is presented in the same order: measurement conditions, figures or fitted values, and a short interpretation of the observed trends.

==X-Ray Reflectivity (XRR) analysis==

XRR measurements were performed using a Rigaku SmartLab X-ray diffractometer. The Cu X-ray tube was operated at 40 kV and 30 mA. The incident optics included an IPS (incident parallel-slit) adapter with a 5° Soller slit. The slit configuration was IS = 0.05 mm, RS1 = 0.05 mm and RS2 = 0.075 mm. Scans were acquired with a step size of 0.01° and a counting time of 2 s per point.

XRR provides information from the critical-angle region and interference fringes. Their positions and damping were modelled to obtain film thickness, scattering-length-density-related mass density and interface/surface roughness. Fitting was carried out in SmartLab Studio. The model contained an effective Si-based substrate, a possible interfacial Si–metal-containing layer where required by the data, the deposited VNx film and a thin, low-density surface overlayer attributed to oxidation and/or adsorbed moisture. The top layer is a phenomenological fit component and should not be interpreted as a chemically pure water layer.

<gallery caption="" widths="400px" heights="350px" perrow="2">
image:eves XRR 600C Vanadium Nitride reactive p-DC PC1 src5.png|Measured and fitted XRR curves for the VNx series deposited at 600 °C. The fringe period changes systematically with film thickness.
image:eves XRR 400C Vanadium Nitride reactive p-DC PC1 src5.png|Measured and fitted XRR curves for the VNx series deposited at 400 °C. The increasingly wide fringe spacing is consistent with decreasing film thickness at higher N2 fraction.
</gallery>

===Extracted values===

The values below are fit results and should be interpreted as model-dependent effective parameters. Thickness is generally the most robust XRR result. Density and roughness may be correlated with each other and with the assumed surface and interface layers, especially for comparatively thick or rough films.

{| border="2" cellspacing="2" cellpadding="3" colspan="10"
|bgcolor="#B1FB17" |'''XRR results for VNx layers deposited at 400 °C'''
|-
|

{| {{table}}
| align="center" |
{| border="2" cellspacing="2" cellpadding="3" align="center" style="width:1500px"

|-
!colspan="1" style="background:silver; color:black;" align="center" |
|colspan="3" style="background:silver; color:black;" align="center" |Top layer (moisture)
|colspan="3" style="background:silver; color:black;" align="center" |VNx Main layer
|colspan="3" style="background:silver; color:black;" align="center" |Si wafer with 300 nm thermal oxide

|-
!style="background:WhiteSmoke; color:black;" align="center" |Deposition name
|style="background:WhiteSmoke; color:black;" align="center" |VNx/Moisture thickness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |VNx/Moisture density (g/cm3)
|style="background:WhiteSmoke; color:black;" align="center" |VNx/Moisture roughness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |VNx thickness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |VNx density (g/cm3)
|style="background:WhiteSmoke; color:black;" align="center" |VNx roughness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |Si thickness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |Si density (g/cm3)
|style="background:WhiteSmoke; color:black;" align="center" |Si roughness (nm)

|-
|style="background:White;" |wafer 2
|style="background:White;" |0.148
|style="background:White;" |1.013
|style="background:White;" |2.454
|style="background:White;" |250.928
|style="background:White;" |5.448
|style="background:White;" |4.171
|style="background:White;" |<math>\infty</math>
|style="background:White;" |2.3360
|style="background:White;" |0.141

|-
|style="background:White;" |wafer 3
|style="background:White;" |0.525
|style="background:White;" |0.854
|style="background:White;" |2.922
|style="background:White;" |199.401
|style="background:White;" |5.555
|style="background:White;" |4.992
|style="background:White;" |<math>\infty</math>
|style="background:White;" |2.3360
|style="background:White;" |0.151

|-
|style="background:White;" |wafer 4
|style="background:White;" |0.729
|style="background:White;" |0.609
|style="background:White;" |2.979
|style="background:White;" |167.250
|style="background:White;" |5.541
|style="background:White;" |5.524
|style="background:White;" |<math>\infty</math>
|style="background:White;" |2.3360
|style="background:White;" |0.225

|-
|style="background:White;" |wafer 5
|style="background:White;" |1.002
|style="background:White;" |0.850
|style="background:White;" |2.633
|style="background:White;" |149.104
|style="background:White;" |5.613
|style="background:White;" |5.008
|style="background:White;" |<math>\infty</math>
|style="background:White;" |2.3360
|style="background:White;" |0.372

|-
|}
|-
|}
|}

{| border="2" cellspacing="2" cellpadding="3" colspan="10"
|bgcolor="#B1FB17" |'''XRR results for VNx layers deposited at 600 °C'''
|-
|

{| {{table}}
| align="center" |
{| border="2" cellspacing="2" cellpadding="3" align="center" style="width:1500px"

|-
!colspan="1" style="background:silver; color:black;" align="center" |
|colspan="3" style="background:silver; color:black;" align="center" |Top layer (moisture)
|colspan="3" style="background:silver; color:black;" align="center" |VNx Main layer
|colspan="3" style="background:silver; color:black;" align="center" |Si substrate

|-
!style="background:WhiteSmoke; color:black;" align="center" |Deposition name
|style="background:WhiteSmoke; color:black;" align="center" |VNx/Moisture thickness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |VNx/Moisture density (g/cm3)
|style="background:WhiteSmoke; color:black;" align="center" |VNx/Moisture roughness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |VNx thickness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |VNx density (g/cm3)
|style="background:WhiteSmoke; color:black;" align="center" |VNx roughness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |Si thickness (nm)
|style="background:WhiteSmoke; color:black;" align="center" |Si density (g/cm3)
|style="background:WhiteSmoke; color:black;" align="center" |Si roughness (nm)

|-
|style="background:White;" |wafer 7
|style="background:White;" |1.106
|style="background:White;" |1.184
|style="background:White;" |2.988
|style="background:White;" |218.010
|style="background:White;" |5.705
|style="background:White;" |4.106
|style="background:White;" |<math>\infty</math>
|style="background:White;" |2.3360
|style="background:White;" |0.104

|-
|style="background:White;" |wafer 8
|style="background:White;" |1.196
|style="background:White;" |0.600
|style="background:White;" |1.499
|style="background:White;" |187.549
|style="background:White;" |5.703
|style="background:White;" |4.274
|style="background:White;" |<math>\infty</math>
|style="background:White;" |2.3360
|style="background:White;" |0.107

|-
|style="background:White;" |wafer 9
|style="background:White;" |0.327
|style="background:White;" |0.639
|style="background:White;" |1.477
|style="background:White;" |161.297
|style="background:White;" |5.938
|style="background:White;" |3.900
|style="background:White;" |<math>\infty</math>
|style="background:White;"|2.3360
|style="background:White;" |0.236

|-
|style="background:White;" |wafer 10
|style="background:White;" |0.644
|style="background:White;" |0.610
|style="background:White;" |1.499
|style="background:White;" |144.469
|style="background:White;" |5.891
|style="background:White;" |3.660
|style="background:White;" |<math>\infty</math>
|style="background:White;" |2.3360
|style="background:White;" |0.526

|-
|}
|-
|}
|}

The fitted VNx thickness decreases monotonically with increasing N2 fraction at both temperatures, confirming the deposition-rate trend in the performance table. For wafers 2–5, the fitted thickness falls from 250.928 to 149.104 nm; for wafers 7–10, it falls from 218.010 to 144.469 nm.

The fitted main-layer density is approximately 5.45–5.61 g/cm3 for the 400 °C series and 5.70–5.94 g/cm3 for the 600 °C series. Within the limitations of the model, the higher values at 600 °C suggest denser film growth. The fitted roughness of the main layer is approximately 4.17–5.52 nm at 400 °C and 3.66–4.27 nm at 600 °C, suggesting somewhat smoother layers at the higher temperature. These conclusions are comparative; they depend on the selected layer stack and should not be treated as independent chemical identification.

==Grazing-incidence X-ray diffraction (GiXRD)==

GiXRD measurements were performed on the VNx-coated Si/SiO2 wafers using a Rigaku SmartLab diffractometer with a Cu sealed X-ray tube operated at 40 kV and 30 mA. The scans covered a 2θ range of 30–80°, using a 0.5 mm incident slit, a step size of 0.01° and a scan speed of 2°/min. The incident angle was fixed at <math>\omega=2^\circ</math> relative to the sample surface throughout the measurement. This shallow fixed-incidence geometry increases the relative contribution from the deposited film, although contributions from the substrate and interface may still be present. Peak positions were compared with reference patterns from the Crystallography Open Database (COD).

The measurements reveal the same general phase evolution at both deposition temperatures. At 5% N2, the patterns are dominated by reflections tentatively assigned to β-V2Si. At 10% N2, reflections from both β-V2Si and cubic VN are observed. When the N2 fraction is increased to 15–25%, cubic VN becomes the dominant crystalline phase. Within the investigated parameter range, the reactive-gas fraction therefore has the clearest effect on the phase development, while increasing the deposition temperature from 400 to 600 °C does not change the overall phase sequence.

The phase assignments are qualitative. Film texture, overlapping reflections and possible substrate or interface contributions can influence the observed relative intensities; consequently, the GiXRD patterns should not be used to estimate quantitative phase fractions without further analysis.

==Additional characterization and complete results==

A complete GiXRD description, including the original diffraction patterns and detailed peak assignments, together with the full XPS composition analysis, REELS results and supporting figures, is available on the corresponding internal LabIntra page. For further information, access to the complete data set or a discussion of the results, please contact Evgeniy Shkondin, DTU Nanolab.

Specific Process Knowledge/Thin film deposition/Deposition of Vanadium Nitride

Eves — Tue, 13 Oct 2026 17:01:47 GMT

Deposition of Tungsten Nitride

← Older revision		Revision as of 18:01, 13 October 2026
(5 intermediate revisions by the same user not shown)
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	== Deposition of Tungsten Nitride ==		== Deposition of Tungsten Nitride ==

	Deposition of WN<sub>x</sub> can only be done by reactive sputtering using W target.		Deposition of VN<sub>x</sub> can only be done by reactive sputtering using a V target.

	The tool of choice for this application is the Cluster-based multi-chamber high vacuum sputtering deposition system, commonly referred to as the "[[Specific Process Knowledge/Thin film deposition/Cluster-based multi-chamber high vacuum sputtering deposition system\|Cluster Lesker]]." The operating process is described in detail.:		The tool of choice for this application is the Cluster-based multi-chamber high-vacuum sputtering deposition system, commonly referred to as the "[[Specific Process Knowledge/Thin film deposition/Cluster-based multi-chamber high vacuum sputtering deposition system\|Cluster Lesker]]." The operating process is described in detail.:



	* [[Specific Process Knowledge/Thin film deposition/Deposition of Vanadium Nitride/VN Reactive Sputtering in Cluster Lesker PC1\|Deposition of Vanadium Nitride (VN<sub>x></sub>) using reactive pulsed DC sputtering]] in Sputter-System Metal-Oxide(PC1) Source 5 (3-inch target)		* [[Specific Process Knowledge/Thin film deposition/Deposition of Vanadium Nitride/VN Reactive Sputtering in Cluster Lesker PC1\|Deposition of Vanadium Nitride (VN<sub>x</sub>) using reactive pulsed DC sputtering in Sputter-System Metal-Oxide(PC1) Source 5 (3-inch target)]]


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	\|-style="background:silver; color:black"		\|-style="background:silver; color:black"
	!		!
			![[Specific_Process_Knowledge/Thin_film_deposition/Cluster-based_multi-chamber_high_vacuum_sputtering_deposition_system\|Sputter-System Metal-Nitride(PC1)]]
	![[Specific_Process_Knowledge/Thin_film_deposition/Cluster-based_multi-chamber_high_vacuum_sputtering_deposition_system\|Sputter-System Metal-Nitride(PC3)]]		![[Specific_Process_Knowledge/Thin_film_deposition/Cluster-based_multi-chamber_high_vacuum_sputtering_deposition_system\|Sputter-System Metal-Nitride(PC3)]]
	~~![[Specific Process Knowledge/Thin film deposition/Lesker\|Lesker sputter system]]~~
	\|-		\|-

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	!Generel description		!Generel description
	\|		\|
	*reactive ~~DC/~~Pulsed DC		*reactive Pulsed DC
	*reactive HIPIMS (high-power impulse magnetron sputtering)		*reactive HIPIMS (high-power impulse magnetron sputtering)
	\|		\|
	*reactive DC sputtering ~~(not tested~~)		*reactive Pulsed DC
			*reactive HIPIMS (high-power impulse magnetron sputtering)
	\|-		\|-

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	\|		\|
	*Limited by process time.		*Limited by process time.
	*Deposition rate (0.2 nm/s) ~~is likely faster than Sputter-System (Lesker)~~		*Deposition rate around 0.1 nm/s) depends on Ar/N<sub>2</sub> ratio and power.

	\|		\|
	*Limited by process time.		*Limited by process time.
	*Deposition rate ~~unknown~~		*Deposition rate around 0.1 nm/s) depends on Ar/N<sub>2</sub> ratio and power.
	\|-		\|-

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	*Up to 600 °C		*Up to 600 °C
	\|		\|
	*Up to ~~400~~ °C ~~(Room temperature from 2021)~~		*Up to 600 °C
	\|-		\|-

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	*Some step coverage possible		*Some step coverage possible
	\|		\|
	*Some step coverage possible ~~but amount unknown~~		*Some step coverage possible
	\|-		\|-

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	\|		\|
	*Deposition on one side of the substrate		*Deposition on one side of the substrate
	*Properties including tunable stoichiometry ~~(requires process development)~~		*Properties including tunable stoichiometry
	\|		\|
	*Deposition on one side of the substrate		*Deposition on one side of the substrate
	*~~Unknown quality~~		*Properties including tunable stoichiometry
	*Likely O-contamination
	\|-		\|-

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	\|		\|
	*Many smaller samples		*Many smaller samples
	Up to 10100 mm or 150 mm wafers		*Up to 10 100 mm or 150 mm wafers
	\|		\|
	*~~Several~~ smaller samples		*Many smaller samples
	*~~1-several 50 mm wafers~~		*Up to 10 100 mm or 150 mm wafers
	~~1~~100 mm ~~wafers~~
	~~1~~150 mm ~~wafer~~
	\|-		\|-

Specific Process Knowledge/Thin film deposition/Deposition of Vanadium Nitride

Eves — Tue, 13 Oct 2026 16:55:03 GMT

Created page with "{{cc-nanolab}} '''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php?title=Specific_Process_Knowledge/Thin_film_deposition/Deposition_of_Tungsten_Nitride&action=submit click here]''' =Vanadium Nitride (WNx)= Tungsten nitride (WNₓ, commonly W₂N or δ‑WN) is a refractory ceramic that combines very high melting temperature, extreme hardness, chemical inertness, a..."

New page

{{cc-nanolab}}

'''Feedback to this page''': '''[mailto:labadviser@nanolab.dtu.dk?Subject=Feed%20back%20from%20page%20http://labadviser.nanolab.dtu.dk/index.php?title=Specific_Process_Knowledge/Thin_film_deposition/Deposition_of_Tungsten_Nitride&action=submit click here]'''

=Vanadium Nitride (WNx)=

Tungsten nitride (WNₓ, commonly W₂N or δ‑WN) is a refractory ceramic that combines very high melting temperature, extreme hardness, chemical inertness, and good electrical conductivity in a composition‑tunable, CMOS‑compatible matrix.
Thin films are produced chiefly by reactive magnetron sputtering, where nitrogen flow and substrate temperature set stoichiometry and phase, yielding dense layers with controllable resistivity and stress.
In semiconductor process flows, WNₓ acts as a robust Cu diffusion barrier/liner, hard mask, gate or contact material, and precision thin‑film resistor; its high absorption coefficient also makes it the standard absorber layer in EUV lithography photomasks and a candidate for x‑ray mask blanks.
Optically, WN-based stacks offer durable, high-temperature plasmonic and thermally emissive coatings, mid-IR absorbers, and multilayer structures for soft-x-ray mirrors and synchrotron beamline optics, delivering stability far beyond noble metals under extreme photon flux.
Beyond electronics and photonics, the material’s wear and oxidation resistance support MEMS springs, high‑temperature sensors, and corrosion‑resistant coatings, while select WN phases become superconducting below roughly 3–5 K, enabling niche low‑loss microwave resonators and detector elements that benefit from its mechanical robustness and diffusion‑barrier capability.

== Deposition of Tungsten Nitride ==

Deposition of WNx can only be done by reactive sputtering using W target.

The tool of choice for this application is the Cluster-based multi-chamber high vacuum sputtering deposition system, commonly referred to as the "[[Specific Process Knowledge/Thin film deposition/Cluster-based multi-chamber high vacuum sputtering deposition system|Cluster Lesker]]." The operating process is described in detail.:

* [[Specific Process Knowledge/Thin film deposition/Deposition of Vanadium Nitride/VN Reactive Sputtering in Cluster Lesker PC1|Deposition of Vanadium Nitride (VNx>) using reactive pulsed DC sputtering]] in Sputter-System Metal-Oxide(PC1) Source 5 (3-inch target)

At the moment (October 2026), we have a 3-inch V target (0.125" thick) for PC3 or PC1.

==Comparison of sputter systems for reactive deposition==

{|border="1" cellspacing="1" cellpadding="3" style="text-align:left;"
|-

|-
|-style="background:silver; color:black"
!
![[Specific_Process_Knowledge/Thin_film_deposition/Cluster-based_multi-chamber_high_vacuum_sputtering_deposition_system|Sputter-System Metal-Nitride(PC3)]]
![[Specific Process Knowledge/Thin film deposition/Lesker|Lesker sputter system]]
|-

|-
|-style="background:WhiteSmoke; color:black"
!Generel description
|
*reactive DC/Pulsed DC
*reactive HIPIMS (high-power impulse magnetron sputtering)
|
*reactive DC sputtering (not tested)
|-

|-
|-style="background:LightGrey; color:black"
!Stoichiometry
|
*Tunable
|
*Tunable
|-

|-
|-style="background:WhiteSmoke; color:black"
!Film thickness
|
*Limited by process time.
*Deposition rate (0.2 nm/s) is likely faster than Sputter-System (Lesker)

|
*Limited by process time.
*Deposition rate unknown
|-

|-
|-style="background:LightGrey; color:black"
!Process temperature
|
*Up to 600 °C
|
*Up to 400 °C (Room temperature from 2021)
|-

|-
|-style="background:WhiteSmoke; color:black"
!Step coverage
|
*Some step coverage possible
|
*Some step coverage possible but amount unknown
|-

|-
|-style="background:LightGrey; color:black"
!Film quality
|
*Deposition on one side of the substrate
*Properties including tunable stoichiometry (requires process development)
|
*Deposition on one side of the substrate
*Unknown quality
*Likely O-contamination
|-

|-
|-style="background:WhiteSmoke; color:black"
!Batch size
|
*Many smaller samples
*Up to 10*100 mm or 150 mm wafers
|
*Several smaller samples
*1-several 50 mm wafers
*1*100 mm wafers
*1*150 mm wafer
|-

|-
|-style="background:LightGrey; color:black"
!'''Allowed materials'''
|
*Almost any as long as they do not outgas and are not very toxic, see cross-contamination sheets
|
*Almost any as long as they do not outgas and are not very toxic, see cross-contamination sheets
|-
|}

Specific Process Knowledge/Thin film deposition

Eves — Tue, 13 Oct 2026 16:52:21 GMT

Choose material to deposit

← Older revision		Revision as of 17:52, 13 October 2026
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	[[/Deposition of Tungsten Nitride\| Tungsten Nitride (W<sub>x</sub>N<sub>y</sub>)]]<br/>		[[/Deposition of Tungsten Nitride\| Tungsten Nitride (W<sub>x</sub>N<sub>y</sub>)]]<br/>
	[[/Deposition of Tantalum Nitride\| Tantalum Nitride (Ta<sub>x</sub>N<sub>y</sub>)]]<br/>		[[/Deposition of Tantalum Nitride\| Tantalum Nitride (Ta<sub>x</sub>N<sub>y</sub>)]]<br/>
			[[/Deposition of Vanadium Nitride\| Vanadium Nitride (VN<sub>x</sub>)]]<br/>

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LabAdviser/LabManager

Thes — Fri, 09 Oct 2026 09:13:58 GMT

Orderlines in LM

← Older revision		Revision as of 10:13, 9 October 2026
(11 intermediate revisions by the same user not shown)
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	When you use the cleanroom, use equipment or buy wafers your project or department will be charged according to the DTU Nanolab pricebook. You can review the charges if you click the "Orderlines" in the LabManager main menu. Note for the cost indicated is the cost for commercial activities. The actual cost charged depends on what kind of project your are working on. See the DTU Nanolab pricebook for details.		When you use the cleanroom, use equipment or buy wafers your project or department will be charged according to the DTU Nanolab pricebook. You can review the charges if you click the "Orderlines" in the LabManager main menu. Note for the cost indicated is the cost for commercial activities. The actual cost charged depends on what kind of project your are working on. See the DTU Nanolab pricebook for details.
	You have the possibility to correct the orderline e.g. if it is charged on the wrong project or you had forgot to log out of a tool. Click on the [Change] field to the right of the line. A new line opens where you can edit the amount, project, text or date. If you edit the amount the change has to be acknowledged by Nanolab first.
			You have the possibility to [[LabAdviser/LabManager/Guide - change orderlines \|correct the orderline ]] e.g. if it is charged on the wrong project or you had forgot to log out of a tool.
			<!--Click on the [Change] field to the right of the line. A new line opens where you can edit the amount, project, text or date. If you edit the amount the change has to be acknowledged by Nanolab first.

	===Change orderlines===		===Change orderlines===
	Lab activities are registered in LabManager orderlines. If you forget to stop your equipment usage - or an orderline is incorrect for another reason - you can request a change. ~~Follow this small [[LabAdviser/LabManager/Guide~~ - ~~change orderlines \|guide ]].~~		Lab activities are registered in LabManager orderlines. If you forget to stop your equipment usage - or an orderline is incorrect for another reason - you can request a change.-->

	=== Logbooks in LM ===		=== Logbooks in LM ===
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	*YELLOW means: The equipment is under service. You are ''under no circumstances allowed'' to use the equipment.		*YELLOW means: The equipment is under service. You are ''under no circumstances allowed'' to use the equipment.
	*GREEN means: Someone is logged in. You are able to use the equipment, but make sure it is you that is logged in.		*GREEN means: Someone is logged in. You are able to use the equipment, but make sure it is you that is logged in.

			<div style="clear:both;"></div>



	=== Purchase of wafers ===		=== Purchase of wafers ===
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	=== General info ===		=== General info ===

	You can find important information about the clean room in LabManager here: [http://labmanager.dtu.dk/function.php?module=Machine&view=generalinfo&page_id=64\| Documents with General Information]<!--As of September 2022 it contains:		You can find important information about the clean room in LabManager here: [http://labmanager.dtu.dk/function.php?module=Machine&view=generalinfo&page_id=64\| Documents with General Information]

			<!--As of September 2022 it contains:

	Safety Documents:		Safety Documents:

← Older revision		Revision as of 18:21, 13 October 2026
(One intermediate revision by the same user not shown)
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	[[/Deposition of NiFe\|NiFe]]<br/>		[[/Deposition of NiFe\|NiFe]]<br/>
	[[/Deposition of NiV\|NiV]] alloy <br/>		[[/Deposition of NiV\|NiV]] alloy <br/>
			[[/Deposition of V3Si\|V<sub>3</sub>Si]] alloy <br/>
	[[/Deposition of TiW\|TiW]] alloy (10%/90% by weight) <br/>		[[/Deposition of TiW\|TiW]] alloy (10%/90% by weight) <br/>
	[[/Deposition of MoSi\|MoSi]] alloy (50%/50% by At.%) <br/>		[[/Deposition of MoSi\|MoSi]] alloy (50%/50% by At.%) <br/>

← Older revision		Revision as of 17:52, 13 October 2026
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	[[/Deposition of Tungsten Nitride\| Tungsten Nitride (W<sub>x</sub>N<sub>y</sub>)]]<br/>		[[/Deposition of Tungsten Nitride\| Tungsten Nitride (W<sub>x</sub>N<sub>y</sub>)]]<br/>
	[[/Deposition of Tantalum Nitride\| Tantalum Nitride (Ta<sub>x</sub>N<sub>y</sub>)]]<br/>		[[/Deposition of Tantalum Nitride\| Tantalum Nitride (Ta<sub>x</sub>N<sub>y</sub>)]]<br/>
			[[/Deposition of Vanadium Nitride\| Vanadium Nitride (VN<sub>x</sub>)]]<br/>

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