View source for Specific Process Knowledge/Etch/AOE (Advanced Oxide Etch)

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== Etching using the dry etch technique AOE (Advanced oxide etch) ==
[[Image:AOE.jpg|300x300px|thumb|AOE: positioned in cleanroom B-1]]

The AOE can be used for dry etching silicon oxide, silicon (oxy)nitride and quartz. Look in the manuals for the AOE to see how to operate the machine (you can find the manuals in LabManager on the AOE page).


'''The user manual, quality control procedure and results, user APV, technical information and contact information can be found in LabManager:''' 
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<!-- give the link to the equipment info page in LabManager: -->
[http://labmanager.danchip.dtu.dk/function.php?module=Machine&view=view&mach=115  AOE in LabManager]

== Process information ==

*[[Specific Process Knowledge/Etch/Etching of Silicon Oxide/SiO2 etch using AOE|Etch of Silicon Oxide using AOE]]
*[[/Si etch using AOE|Si etch using AOE]]
*[[/Remove resist in the AOE|Remove resist in the AOE]]
*[[Specific Process Knowledge/Etch/Etching of Bulk Glass/AOE etching of fused silica|Fused silica etch using AOE]]
*[[/Quartz etch using AOE|Quartz etch using AOE - special very thick samples]]
*[[/Silicon Nitride Etch using AOE|Silicon Nitride Etch using AOE]]

===Limitations using the AOE===
====Wafer bow====
There is a limit to how much the wafer can bow and still be clamped on the chuck. The limit can maybe vary a little over time and may also depend on the material on the backside of the substrate. On a 100mm Si wafer with SiO2 on the backside (<10µm) we expect the limit to be around 50µm bow (when the back side surface is convex).

A bow will be created when etching the top oxide layer on a wafer with oxide on both sides. For a larger etch load the bow will be more severe for a specific etch depth when for a smaller etch load. I have been able to etch much deeper in SiO2 with a P-Si mask than with a photo resist mask on a wafer with 50% load. When using photoresist the wafer stopped clamping during the etch after just a few µm. With P-Si I could etch 15µm without problems. I expect this to be due to a combination of P-Si on the back side clamping much better and P-Si on the back side helping to reduce the bow.

====Transparent wafers====
Transparent wafers are a challange for two reasons. 1. In the load lock the LASER detection system that is used to detect the wafer during mapping cannot detect a completely transparent wafer. 2. A transparent wafer is either quartz or fused silicon. These materials are very difficult to clamp electrostatically and will therefore not be able to pass the He leak up test succesfully. 
# The first issue may be overcome by using a non-transparent masking material or adding a non-transparent material on the back side of the wafer (could be aluminium).
#The second issue may be overcome by reducing the He back side pressure or reducing the He back side cooling completely. Another way to solve it is to either bond the transparent wafer to a silicon wafer before transfering it into chamber or deposite a more conducting layer on the backside of the wafer. This could be aluminium but also 1-2µm P-Si may be enough.

==A rough overview of the performance of AOE and some process related parameters==

{| border="2" cellspacing="0" cellpadding="10" 
|-
!style="background:silver; color:black;" align="left"|Purpose 
|style="background:LightGrey; color:black"|Dry etch of 
|style="background:WhiteSmoke; color:black"|
*Silicon oxide
*Silicon (oxy)nitride
*Quartz
*Silicon mask etching
|-
!style="background:silver; color:black" align="left" valign="top" rowspan="2"|Performance
|style="background:LightGrey; color:black"|Etch rates
|style="background:WhiteSmoke; color:black"|
~0.5-0.6 µm/min
|-
|style="background:LightGrey; color:black"|Anisotropy
|style="background:WhiteSmoke; color:black"|
*Typical profiles: 86-90 degrees 
|-
!style="background:silver; color:black" align="left" valign="top" rowspan="2"|Process parameter range
|style="background:LightGrey; color:black"|Process pressure
|style="background:WhiteSmoke; color:black"|
*~2-20 mTorr
|-
|style="background:LightGrey; color:black"|Gas flows
|style="background:WhiteSmoke; color:black"|
*C<math>_4</math>F<math>_8</math>: 0-40 sccm
*O<math>_2</math>: 0-100 sccm
*CF<math>_4</math>: 0-100 sccm
*H<math>_2</math>: 0-30 sccm
*He: 0-500 sccm
*N<math>_2</math>: 0-1000 sccm
*SF<math>_6</math>: 0-300 sccm
|-
!style="background:silver; color:black" align="left" valign="top" rowspan="3"|Substrates
|style="background:LightGrey; color:black"|Batch size
|style="background:WhiteSmoke; color:black"|
*1 6" wafer per run (only when the system is setup to 6")
*1 4" wafer per run
*1 2" wafer per run (needs carrier)
*Or several smaller pieces (needs carrier)
|-
| style="background:LightGrey; color:black"|Substrate material allowed
|style="background:WhiteSmoke; color:black"|
*Silicon with layers of silicon oxide or silicon (oxy)nitride
*Quartz wafers 
|- 
| style="background:LightGrey; color:black"|Possible masking material
|style="background:WhiteSmoke; color:black"|
*Photoresist/e-beam resist
*Silicon/PolySi
*Aluminium
*Chromium
|- 
|}